Maxim-integrated MAXQ Family User Manual

Functional DiagramsPin Configurations appear at end of data sheet.Functional Diagrams continued at end of data sheet.UCSP is a trademark of Maxim Inte

2-52.2 Register SpaceThe MAXQ architecture provides a total of 16 register modules. Each of these modules contains 32 registers. The first eight regis

9-22MAXQ Family User’s Guide9.5.2.2 Receive Pin SamplingWhen IREN = 1 and IRTX = 0, the IR hardware supports the T2H register counting of internal T2L

9-23MAXQ Family User’s Guide9.6 IR Peripheral Register9.6.1 Infrared Control Register (IRCN)Bits 7 to 3: ReservedBit 2: Infrared Subcarrier Enable (IR

10-1MAXQ Family User’s GuideSECTION 10: SERIAL I/O MODULEThis section contains the following information:10.1 UART Modes . . . . . . . . . . . . . .

10-2MAXQ Family User’s GuideSECTION 10: SERIAL I/O MODULEThe Serial I/O Module provides the MAXQ access to a universal asynchronous receiver/transmitt

10-3MAXQ Family User’s GuideDIVIDEBY 12D7D6D5D4D3D2D1D0LOADCLOCKOUTPUT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRRDD7D6D5D4D3D2D1D0CLOCKRECEIVE

10-4MAXQ Family User’s Guide10.1.2 UART Mode 1This mode provides asynchronous, full-duplex communication. A total of 10 bits is transmitted, consistin

10-5MAXQ Family User’s GuideDIVIDEBY 4D7D6D5D4D3D2D1D001LOADCLOCKTRANSMIT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRSBUFRDD7D6D5D4D3D2D1D0CLOCKR

10-6MAXQ Family User’s GuideDIVIDEBY 2D7D6D5D4D3D2D1D001LOADCLOCKTRANSMIT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRSBUFRDD7D6D5D4D3D2D1D0CLOCKR

10.1.4 UART Mode 3This mode has the same operation as Mode 2, except for the baud-rate source. As shown in Figure 10-4, Mode 3 generates baud ratesthr

10.2 Baud-Rate GenerationEach mode of operation has a baud-rate generator associated with it. The baud-rate generation techniques are affected by cert

2-6MAXQ Family User’s Guide2.3 Memory OrganizationBeyond the internal register space, memory on the MAXQ microcontroller is organized according to a H

Table 10-3. Example Baud-Clock Generator Settings (SMOD = 1)10.3 Framing Error DetectionA framing error occurs when a valid stop bit is not detected.

10.4 UART Peripheral Registers10.4.1 Serial Control Register (SCON)Bit 7: Framing Error Flag (FE). (FEDE = 1) This bit is set upon detection of an inv

10-11MAXQ Family User’s Guide10.4.2 Serial Port Mode Register (SMD)Bits 7 to 3: ReservedBit 2: Framing Error Detection Enable (FEDE). This bit selects

11-1MAXQ Family User’s GuideSECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULEThis section contains the following information:11.1 SPI Transfer Form

11-2MAXQ Family User’s GuideSECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULEThe serial peripheral interface (SPI) module of the MAXQ microcontroll

11.1 SPI Transfer FormatsDuring an SPI transfer, data is simultaneously transmitted and received over two serial data lines with respect to a single s

11-4MAXQ Family User’s Guide11.3 SPI Transfer Baud RatesWhen operating as a slave device, an external master drives the SPI serial clock. For proper s

11.4.3 Write Collision While BusyA write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY = 1). Sinc

11.7 SPI Peripheral Registers11.7.1 SPI Control Register (SPICN)Bit 7: SPI Transfer Busy Flag (STBY). This bit is used to indicate the current transmi

11-7MAXQ Family User’s GuideBit 0: SPI Enable (SPIEN)0 = SPI module and its baud-rate generator are disabled1 = SPI module and its baud-rate generator

2-7post increment/decrement source pointers by a MOVE instruction or pre increment/decrement destination pointers by a MOVE instruc-tion. Using Data P

11.7.4 SPI Data Buffer Register (SPIB)Bits 15 to 0: SPI Data Buffer (SPIB.[15:0]). Data for SPI is read from or written to this location. The serial t

12-1MAXQ Family User’s GuideSECTION 12: HARDWARE MULTIPLIER MODULEThis section contains the following information:12.1 Hardware Multiplier Organizatio

12-2MAXQ Family User’s GuideSECTION 12: HARDWARE MULTIPLIER MODULEThe hardware multiplier module can be used by the MAXQ microcontroller to support hi

12.2 Hardware Multiplier ControlsThe selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register:

12.4.1 Accessing the Multiplier There are no restrictions on how quickly data is entered into the operand registers or the order of data entry. The on

Bit 4: Square Function Enable (SQU). This bit supports the hardware square function. When this bit is set to logic 1, a square oper-ation is initiated

12-6MAXQ Family User’s Guide12.5.3 Multiplier Operand B Register (MB)Bits 15 to 0: Multiplier Operand B Register (MB.[15:0]). This operand B register

12-7MAXQ Family User’s Guide12.5.5 Multiplier Accumulator 1 Register (MC1)Bits 15 to 0: Multiplier Accumulator 1 Register (MC1.[15:0]). The MC1 regist

12.5.7 Multiplier Read Register 1 (MC1R)Bits 15 to 0: Multiplier Read Register 1 (MC1R.[15:0]). The MC1R register represents bytes 3 and 2 result from

12.6 Hardware Multiplier ExamplesThe following are code examples of multiplier operations.;Unsigned Multiply 16-bit x 16-bitmove MCNT, #21h ; CLD=1,

2-8MAXQ Family User’s Guidepage (16kWords) may be logically mapped, as just defined, to either the upper or lower half of data memory. If word access

13-1MAXQ Family User’s GuideSECTION 13: 1-Wire BUS MASTERThis section contains the following information:13.1 1-Wire Peripheral Registers . . . . . .

13-2MAXQ Family User’s GuideSECTION 13: 1-Wire BUS MASTERThe 1-Wire Bus Master can be used by the MAXQ microcontroller to support 1-Wire communication

13.1 1-Wire Peripheral RegistersThe MAXQ microcontroller interfaces to the 1-Wire Bus Master through two peripheral registers: 1-Wire Master Address (

13.2 1-Wire Clock ControlAll 1-Wire timing patterns are generated using a base clock of 1.0MHz. To create this base clock frequency, the 1-Wire Bus Ma

13.3 1-Wire Bus Master ControlThe 1-Wire Bus Master can perform certain special functions to support OW line operation. These special functions can be

13.4 1-Wire Bus Master Commands The 1-Wire Bus Master can generate special commands on the 1-Wire bus in addition to transmitting and receiving data.

Table 13-2. ROM ID Read Time Slot PossibilitiesThe general principle of this search process is to deselect slave devices at every conflicting bit posi

13.5.1 Accelerated ROM Search Example The following example should provide a better understanding of how the Search ROM Accelerator functionality allo

13.6 1-Wire Transmit and Receive OperationsAll data transmitted and received by the 1-Wire Bus Master passes through the transmit/receive data buffer

13.7 1-Wire Bus Master InterruptsThe 1-Wire Bus Master can be configured to generate an interrupt request to the CPU on the occurrence of a number of

2-92.5 Pseudo-Von Neumann Memory AccessThe pseudo-Von Neumann memory mapping is straightforward if there is no memory overlapping among the program, u

13-11MAXQ Family User’s Guide13.7.2 1-Wire Interrupt Enable Register (OWA = 011b)Bit 7: Enable 1-Wire Low Interrupt (EOWL). Setting this bit to logic

13-12MAXQ Family User’s GuideVDDGNDOWOUTINITIALIZATION SEQUENCEOWOUTVDDGNDOWINVDDGNDtRSTLtRSTHtPDHtPDLtPDStWRITE 0 SLOTtWRITE 1 SLOTtLOW1 >1µstLOW0

14-1MAXQ Family User’s GuideSECTION 14: REAL-TIME CLOCK MODULEThis section contains the following information:14.1 RTC Alarm Functions . . . . . . .

14-2MAXQ Family User’s GuideSECTION 14: REAL-TIME CLOCK MODULEThe real-time clock (RTC) is a binary timer that keeps the time of day and provides time

14.1 RTC Alarm FunctionsThe RTC provides time-of-day and sub-second interval alarm functions. The time-of-day alarm, when enabled, occurs based uponma

14-4MAXQ Family User’s GuideVALID FOR ONE 256HzCYCLE EVERY 16SEC.THEN CLEARED TO 0.5-BIT PHASEACCUMULATOR256HzMUX256Hz512HzCARRY-OUTTSGN16-SECOND

14.3 RTC Register AccessSince RTC registers and register bits must be used in the 32kHz clock domain and also be accessible in the system clock domain

14.4 RTC Peripheral Registers14.4.1 RTC Control Register (RCNT)Bit 15: RTC Write Enable (WE). This register bit serves as an additional protection mec

14-7MAXQ Family User’s GuideBit 3: RTC Busy (BUSY). This bit is set to 1 by hardware when any of the following conditions occur: 1) system reset, 2) s

14-8MAXQ Family User’s Guide14.4.3 RTC Seconds Low Register (RTSL)Bits 15 to 0: RTC Seconds Low (RTSL.[15:0]). This register contains the least signif

2-10MAXQ Family User’s GuideWhen executing from the data memory (only allowable when UPA = 0):• Program flows freely between the lower 32k user code (

14-9MAXQ Family User’s Guide14.4.5 RTC Alarm Seconds High Register (RASH)Bits 7 to 4: ReservedBits 3 to 0: RTC Alarm Seconds High (RASH.[3:0]). This r

14.4.7 RTC Sub-Second Alarm Register (RSSA)Bits 15 to 0: RTC Sub-Second Alarm (RSSA.[15:0]). This register contains the reload value for the sub-secon

15-1MAXQ Family User’s GuideSECTION 15: TEST ACCESS PORT (TAP)This section contains the following information:15.1 TAP Controller . . . . . . . . . .

15-2MAXQ Family User’s GuideSECTION 15: TEST ACCESS PORT (TAP)The MAXQ microcontroller incorporates a Test Access Port (TAP) and TAP controller for co

15.2.3 IR-Scan SequenceThe controller state sequence allows instructions (e.g., 'Debug' and 'System Programming') to be shifted in

When the parallel instruction register (IR2:0) is updated, the TAP controller decodes the instruction and performs any necessary oper-ations, includin

15.3 Communication via TAPThe TAP controller is in Test-Logic-Reset state after a power-on-reset. During this initial state, the instruction register

15-6MAXQ Family User’s GuideNEW INSTRUCTIONINSTRUCTION REGISTERTCKTMSTDITDOCONTROLSTATEIR SHIFTREGISTERIR PARALLELOUTPUTREGISTERSELECTEDTDOENABLE

15-7MAXQ Family User’s GuideOLD DATANEW DATADATA REGISTERTCKTMSTDITDOCONTROLSTATESHIFTREGISTERPARALLELOUTPUTINSTRUCTIONREGISTERTDOENABLEDON'

16-1MAXQ Family User’s GuideSECTION 16: IN-CIRCUIT DEBUG MODEThis section contains the following information:16.1 Background Mode Operation . . . . .

2-11Figure 2-5. CDA Functions (Word Access Mode)PHYSICAL DATAx0000x8000x4000DATA MEMORY015CDA1 = 0CDA1 = 1MAXQ20 MEMORY MAP (UPA = 0, EXECUTING FROM U

16-2MAXQ Family User’s GuideSECTION 16: IN-CIRCUIT DEBUG MODEMost MAXQ microcontroller devices are equipped with embedded debug hardware and embedded

The host now can transmit and receive serial data through the 10-bit data shift register that exists between the TDI input and TDO out-put during DR-S

Table 16-1 shows the background mode commands supported by the MAXQ microcontroller. Encodings not listed in this table are notsupported in background

16.1.1 Breakpoint RegistersThe MAXQ microcontroller incorporates six breakpoint registers (BP0-BP5) that are configurable by the host for establishing

16-6MAXQ Family User’s Guide16.1.1.3 Breakpoint 2 Register (BP2)Bits 15 to 0: Breakpoint 2 (BP2.[15:0]). This register is accessible only via backgrou

16.1.1.5 Breakpoint 4 Register (BP4) (REGE = 0)Bits 15 to 0: Breakpoint 4 (BP4.[15:0]). This register is accessible only via background mode read/writ

16.1.1.7 Breakpoint 5 Register (BP5) (REGE = 0)Bits 15 to 0: Breakpoint 5 (BP5.[15:0]). This register is accessible only via background mode read/writ

16-9MAXQ Family User’s Guide16.1.2 Using BreakpointsAll breakpoint registers (BP0-BP5) default to the FFFFh state on power-on reset or when the Test-L

16.2.1 Debug Mode CommandsThe debug engine sets the data shift register status bits to 01b (debug-idle) to indicate that it is ready to accept debug c

16-11MAXQ Family User’s GuideTable 16-2. Debug Mode CommandsOP CODECOMMAND OPERATION0010-0000No Operation No Operation0010-0001Read Register MapRead

2-12MAXQ Family User’s GuideFigure 2-6. CDA Functions (Byte Access Mode)UTILITY ROMPHYSICAL DATAx0000x8000xA000xFFFFx0000x8000xFFFFDATA MEMORYPROGRAM

16.2.2 Read Register Map Command Host-ROM InteractionA read register map command reads out data contents for all implemented system and peripheral reg

allows user code to configure breakpoints that occur inside PMM, thus providing reliable use of debug commands. However, it doesnot allow a good means

16.3.2 In-Circuit Debug Temp 1 Register (ICDT1)Bits 15 to 0: In-Circuit Debug Temp 1 (ICDT1.[15:0]). This register is read/write accessible by the CPU

16.3.4 In-Circuit Debug Flag Register (ICDF)Bits 7 to 4: ReservedBits 3 to 2: Programming Source Select Bits 1:0 (PSS[1:0]). These bits are used to se

16.3.6 In-Circuit Debug Data Register (ICDD)Bits 15 to 0: In-Circuit Debug Data (ICDD.[15:0]). This register is used by the debug engine to store data

17-1MAXQ Family User’s GuideSECTION 17: IN-SYSTEM PROGRAMMING (JTAG)This section contains the following information:17.1 JTAG Bootloader Operation .

17-2MAXQ Family User’s GuideSECTION 17: IN-SYSTEM PROGRAMMING (JTAG)Internal nonvolatile memory of MAXQ microcontrollers can be initialized via Bootst

17.2 Password-Protected AccessSome applications require preventative measures to protect against simple access and viewing of program code memory. To

18-1MAXQ Family User’s GuideSECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARYThis section contains the following information:ADD/ADDC src . . . . . . .

RL/RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-

2-13- Physical program memory pages (P0, P1, P2, P3) are logically mapped into data space based upon the memory segment currently being used for execu

18-3MAXQ Family User’s GuideMNEMONIC DESCRIPTION16-BIT INSTRUCTIONWORDSTATUS BITSAFFECTEDAPINC/DECNOTESAND src Acc ← Acc AND src f001 1010 ssss ssss S

18-4MAXQ Family User’s GuideMNEMONIC DESCRIPTION16-BIT INSTRUCTIONWORDSTATUS BITSAFFECTEDAPINC/DECNOTES{L/S}JUMP src IP ← IP + src or src f000 1100 ss

18-5MAXQ Family User’s GuideADD/ADDC src Add/Add with CarryDescription: The ADD instruction sums the active accumulator (Acc or A[AP]) and the specifi

18-6MAXQ Family User’s GuideMAXQ20 Example(s): ; Acc = 2345h for each exampleADDC A[3] ; A[3] = DCBAh, C=1; → Acc = 0000h, C=1, Z=1, S=0, OV=0ADDC @DP

18-7MAXQ Family User’s GuideAND Acc.<b> Logical AND Carry Flag with Accumulator BitDescription: Performs a logical-AND between the Carry (C) sta

18-8MAXQ Family User’s Guide{L/S}CALL src {Long/Short} Call to SubroutineDescription: Performs a call to the subroutine destination specified by src.

18-9MAXQ Family User’s GuideCMP src Compare AccumulatorDescription: Compare for equality between the active accumulator and the least significant byte

18-10MAXQ Family User’s GuideCPL C Complement Carry FlagDescription: Logically complements the Carry (C) Flag.Status Flags: COperation: C ← ~CEncoding

18-11MAXQ Family User’s Guide{L/S} JUMP src Unconditional {Long/Short} JumpDescription: Performs an unconditional jump as determined by the src specif

18-12MAXQ Family User’s GuideConditional {Long/Short} Jump on Status FlagDescription: Performs conditional branching based upon the state of a specifi

2-14MAXQ Family User’s GuideThe external clock and crystal are mutually exclusive since they are input via the same clock pin. The basic clock source

18-13MAXQ Family User’s GuideJUMP NZ Z=0: IP ← IP + src (relative) -or- src (absolute)Operation: Z=1: IP ← IP + 1Encoding: 150Example(s): JUMP NZ, la

18-14MAXQ Family User’s GuideMOVE dst, src Move DataDescription: Moves data from a specified source (src) to a specified destination (dst). A list of

18-15MAXQ Family User’s GuideMOVE dst, src (continued) Move DataTable 18-3. Destination Specifier CodesData Transfer dst (16-bit) ← src (16-bit): dst

18-16MAXQ Family User’s GuideExample(s): MOVE A[0], A[3] ; A[0] ← A[3]MOVE DP[0], #110h ; DP[0] ← #0110h (PFX[0] register used); MOVE PFX[0], #01h (

18-17MAXQ Family User’s GuideMOVE C, Acc.<b> Move Accumulator Bit to Carry FlagDescription: Replaces the Carry (C) status flag with the specifie

18-18MAXQ Family User’s GuideMOVE C, #1 Set Carry FlagDescription: Sets the Carry (C) processor status flag.Status Flag: C ← 1Operation: C ← 1Encoding

18-19MAXQ Family User’s GuideNEG Negate AccumulatorDescription: Performs a negation (two's complement) of the active accumulator and returns the

18-20MAXQ Family User’s GuideOR Acc.<b> Logical OR Carry Flag with Accumulator BitDescription: Performs a logical-OR between the Carry (C) statu

18-21MAXQ Family User’s GuidePOPI dst Pop Word from the Stack Enable InterruptsDescription: Pops a single word from the stack (@SP) to the specified d

18-22MAXQ Family User’s GuideRET Return from SubroutineDescription: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP) and

2MAXQ Family User’s GuideSECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-15resistor to ensure a satisfactory logic level for active clock pulses. To minimize system noise on the clock circuitry, the external clocksource m

18-23MAXQ Family User’s GuideRET NCOperation: C=0: IP ← @SP--C=1: IP ← IP +1Encoding: 150Example(s): RET NC ; C=1, return (RET) does not occurRET ZOpe

18-24MAXQ Family User’s GuideRETI Return from InterruptDescription: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and

18-25MAXQ Family User’s GuideRETI ZOperation: Z=1: IP ← @SP--INS ← 0Z=0: IP ← IP + 1Encoding: 15 0Example(s): RETI Z ; Z=0, return from interrupt (RET

18-26MAXQ Family User’s Guide(MAXQ10 Version) Rotate Left Accumulator RL/RLC Carry Flag (Ex/In)clusiveDescription: Rotates the active accumulator left

18-27MAXQ Family User’s Guide(MAXQ20 Version) Rotate Left AccumulatorRL/RLC Carry Flag (Ex/In)clusiveDescription: Rotates the active accumulator left

18-28MAXQ Family User’s Guide(MAXQ10 Version) Rotate Right AccumulatorRR/RRC Carry Flag (Ex/In)clusiveDescription: Rotates the active accumulator righ

18-29MAXQ Family User’s Guide(MAXQ20 Version) Rotate Right AccumulatorRR/RRC Carry Flag (Ex/In)clusiveDescription: Rotates the active accumulator righ

18-30MAXQ Family User’s Guide(MAXQ10 Version) Shift Accumulator Left ArithmeticallySLA/SLA2/SLA4 One, Two, or Four TimesDescription: Shifts the active

18-31MAXQ Family User’s Guide(MAXQ20 Version) Shift Accumulator Left ArithmeticallySLA/SLA2/SLA4 One, Two, or Four TimesDescription: Shifts the active

18-32MAXQ Family User’s Guide(MAXQ10 Version) Shift Accumulator Right/SR/SRA/SRA2/SRA4 Shift Accumulator Right ArithmeticallyOne, Two, or Four TimesDe

2-16MAXQ Family User’s Guide2.8 InterruptsThe MAXQ provides a single, programmable interrupt vector (IV) that can be used to handle internal and exter

18-33MAXQ Family User’s GuideSRA2 Operation: 7 Active Acc (Acc) 0 Carry FlagAcc.[5:0] ← Acc.[7:2]Acc.[7:6] ← Acc.7C ← Acc.1Encoding: 15 0Exam

MAXQ Family User’s Guide(MAXQ20 Version) Shift Accumulator Right/SR/SRA/SRA2/SRA4 Shift Accumulator Right ArithmeticallyOne, Two, or Four TimesDescrip

18-35MAXQ Family User’s GuideSRA2 Operation: 15 Active Accumulator (Acc) 0 Carry FlagAcc.[13:0] ← Acc.[15:2]Acc.[15:14] ← Acc.15C ←

18-36MAXQ Family User’s GuideSUB/SUBB src Subtract /Subtract with BorrowDescription: Subtracts the specified src from the active accumulator (Acc) and

18-37MAXQ Family User’s Guide(MAXQ20 Only) Exchange Accumulator BytesXCHDescription: Exchanges the upper and lower bytes of the active accumulator.Sta

18-38MAXQ Family User’s GuideXOR src Logical XORDescription: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified sr

MAXQ Family User’s GuideREVISION HISTORYREVISIONN U MBE RREVISIOND A TEDESCRIPTIONPAGESC H A NGED0 9/04 Or i g inal release. —U pdated Loading a 1 6-b

2-172.8.3 Synchronous vs. Asynchronous Interrupt SourcesInterrupt sources can be classified as either asynchronous or synchronous. All internal interr

2-18MAXQ Family User’s Guide• if the system clock divide ratio is 2, the interrupt request is recognized after 2 system clock;• if the system clock di

2-19Certain MAXQ devices may also incorporate brownout detection capability. For these devices, an on-chip precision reference andcomparator monitor t

2-20MAXQ Family User’s GuideThe PMME bit may not be set to 1 if any potential switchback source is active. Attempts to set the PMME bit under these co

3-1MAXQ Family User’s GuideSECTION 3: PROGRAMMINGThis section contains the following information:3.1 Addressing Modes . . . . . . . . . . . . . . . .

3.8 Handling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-133.8.1 C

3-3MAXQ Family User’s GuideSECTION 3: PROGRAMMINGThe following section provides a programming overview of the MAXQ. For full details on the instructio

3-4MAXQ Family User’s Guide3.3 Reading and Writing RegistersAll functions in the MAXQ are accessed through registers, either directly or indirectly. T

1-1MAXQ Family User’s GuideSECTION 1: OVERVIEWThis section contains the following information:1.1 Instruction Set . . . . . . . . . . . . . . . . . .

3-58-bit destination ← high byte (16-bit source)If, however, we needed to load an 8-bit register with the high byte of a 16-bit source, it would be be

3-6MAXQ Family User’s Guide3.4 Reading and Writing Register BitsThe MOVE instruction can also be used to directly set or clear any one of the lowest 8

3-7• SLA (Arithmetic shift left on active accumulator)• SLA2 (Arithmetic shift left active accumulator two bit positions)• SLA4 (Arithmetic shift left

3-8MAXQ Family User’s GuideFor the modulo increment or decrement operation, the selected range of bits in AP are incremented or decremented. However,

3-93.5.4 ALU Operations Using Only the Active AccumulatorThe following arithmetic and logical operations operate only on the active accumulator.cpl ;

3-10MAXQ Family User’s Guide3.5.7 MAXQ20 Example: Adding Two 4-Byte Numbers Using Auto-Incrementmove A[0], #5678h ; First number – 12345678hmove A[1

3-11• SLA, SLA2, SLA4 (Arithmetic shift left active accumulator)• SRA, SRA2, SRA4 (Arithmetic shift right active accumulator)• SR (Shift active accumu

3-12MAXQ Family User’s Guide3.7.2 Unconditional JumpsAn unconditional jump can be relative (IP +127/-128 words) or absolute (to anywhere in program sp

3-13When the supplied loop address is outside the relative jump range, the prefix register (PFX[0]) is used to supply the high byte of theloop address

3-14MAXQ Family User’s GuideOnce the interrupt handler receives the interrupt, the Interrupt in Service (INS) bit will be set by hardware to block fur

1-2MAXQ Family User’s GuideSECTION 1: OVERVIEWThe MAXQ®family of 16-bit reduced instruction set computing (RISC) microcontrollers is targeted toward l

3-153.9 Accessing the StackThe hardware stack is used automatically by the CALL, RET and RETI instructions, but it can also be used explicitly to stor

3-16MAXQ Family User’s GuideThe Frame Pointer (BP[OFFS]) is actually composed of a base pointer (BP) and an offset from the base pointer (OFFS). For t

3-17The following data pointer related instructions are invalid:move @++DP[0], @DP[0]++move @++DP[1], @DP[1]++move @BP[++Offs], @BP[Offs++]move @--DP[

3-18MAXQ Family User’s GuideIf the timeout is reached without RWT being set, hardware will generate a Watchdog interrupt if the interrupt source has b

3-19Table 3-3. Watchdog Timeout Period SelectionWATCHDOG TIMEOUT(IN NUMBER OF OSCILLATOR CLOCKS)SYSTEM CLOCK MODESYSTEM CLOCKSELECT BITS PMME,CD1, CD0

3-20MAXQ Family User’s GuideBIT POSITIONREGISTER15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0AP — — — — AP (4 bits)APCCLRIDS———MOD2MOD1MOD0PSF Z S—GPF1GPF0OVC

3-21Table 3-6. System Register Bit Reset ValuesNote:Bits marked ‘s’ are static across some or all resets.BIT POSITIONREGISTER15 14 13 12 11 10 9 8 7 6

4-1MAXQ Family User’s GuideSECTION 4: SYSTEM REGISTER DESCRIPTIONSThis section contains the following information:4.1 Accumulator Pointer Register (AP

4-2MAXQ Family User’s GuideSECTION 4: SYSTEM REGISTER DESCRIPTIONSThose registers currently defined in the MAXQ System Register map are described in t

4-3MAXQ Family User’s Guide4.3 Processor Status Flags Register (PSF, 8h[4h])The OV and S bit definitions are given for the MAXQ20 (16-bit accumulators

1-3MAXQ Family User’s Guide• Real-Time Clock• 1-Wire® Bus Master• General-Purpose Digital I/O Ports1.4 MAXQ10 and MAXQ20 MicrocontrollersThis user’s g

4-4MAXQ Family User’s Guide4.6 System Control Register (SC, 8h[8h])Initialization: This register is reset to 100000s0b on all reset. Bit 1 (PWL) is se

4-5MAXQ Family User’s Guide4.8 System Clock Control Register (CKCN, 8h[Eh])Initialization: Bits 4:0 are cleared to zero on all forms of reset. See bit

4-6MAXQ Family User’s Guide4.9 Watchdog Control Register (WDCN, 8h[Fh])Initialization: Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; for

4-7MAXQ Family User’s Guide4.10 (MAXQ10) Accumulator n Register (A[n], 9h[nh])Initialization: This register is cleared to 00h on all forms of reset.Ac

4-8MAXQ Family User’s Guide4.14 Stack Pointer Register (SP, Dh[1h])Bits defined below for 16-word stack depth.Initialization: This register is cleared

4-9MAXQ Family User’s Guide4.19 Data Pointer Control Register (DPC, Eh[4h])Initialization: (MAXQ10) This register is cleared to 0000h on all forms of

4-10MAXQ Family User’s Guide4.23 General Register Byte-Swapped (GRS, Eh[8h])Initialization: This register is cleared to 0000h on all forms of resetAcc

5-1MAXQ Family User’s GuideSECTION 5: PERIPHERAL REGISTER MODULESThe MAXQ microcontroller uses Peripheral Registers to control and monitor peripheral

6-1MAXQ Family User’s GuideSECTION 6: GENERAL-PURPOSE I/O MODULEThis section contains the following information:6.1 I/O Port: Type A . . . . . . . .

6-2MAXQ Family User’s GuideSECTION 6: GENERAL-PURPOSE I/O MODULEThe General-Purpose I/O Module (GPIO) for the MAXQ supports multiple 8-bit port types,

2-1MAXQ Family User’s GuideSECTION 2: ARCHITECTUREThis section contains the following information:2.1 Instruction Decoding . . . . . . . . . . . . .

6.3 I/O Port: Type CThe Type C I/O port is nearly identical to the Type B I/O port, but with the addition of a selectable internal, weak, P-channel, p

6.5 I/O Port Peripheral Registers6.5.1 Port Output x Register (POx)Bits 7 to 0: Port Output x (POx) (POx.[7:0]). This register stores the data that is

6.5.4 (Type A) External Interrupt Enable Register (EIEx)Bit 7: Interrupt 2-5 Edge Select (IT1). This bit selects the edge detection mode for external

6.5.5 (Type A) External Interrupt Flag Register (EIFx)Bits 7 and 6: ReservedBit 5: External Interrupt 5 Flag (IE5). This flag is set when a negative e

Bit 3: Enable External Interrupt 3 (EX3)0 = external interrupt 3 function disabled1 = external interrupt 3 function enabledBit 2: Enable External Inte

6.5.8 (Type D) External Interrupt Edge Select Register (EIESx)Bit 7: Interrupt 7 Edge Select (IT7). This bit selects the edge detection mode for exter

7-1MAXQ Family User’s GuideSECTION 7: TIMER/COUNTER 0 MODULEThis section contains the following information:7.1 Timer 0 . . . . . . . . . . . . . . .

7-2MAXQ Family User’s GuideSECTION 7: TIMER/COUNTER 0 MODULEThe Timer/Counter 0 Module allows the MAXQ to control a 16-bit programmable timer/counter.

7.1.2 Timer 0 Mode: 16-Bit Timer/Counter Setting the T0CN register bits M1:M0 = 01b invokes the 16-bit Timer/Counter operating mode. This mode is iden

7.1.4 Timer 0 Mode: Two 8-Bit Timer/CountersWhen T0CN register bits M1:M0 = 11b, Timer 0 provides two 8-bit timer/counters as shown in Figure 7-3. In

2.9.2 Power Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-192.9.2.1 Switchback . .

7.2 Timer/Counter 0 Peripheral Registers7.2.1 Timer/Counter 0 Control Register (T0CN)Bit 7: Enable Timer 0 Interrupt (ET0). Setting this bit to 1 enab

7.2.2 Timer/Counter 0 High Register (T0H)Bits 7 to 0: Timer/Counter 0 High (T0H.[7:0]). The T0H register is used to load the most significant 8-bit va

8-1MAXQ Family User’s GuideSECTION 8: TIMER/COUNTER 1 MODULEThis section contains the following information:8.1 Timer 1 . . . . . . . . . . . . . . .

8-2MAXQ Family User’s GuideSECTION 8: TIMER/COUNTER 1 MODULEThe Timer/Counter 1 Module allows the MAXQ to control a 16-bit programmable timer/counter.

If the C/T1 bit (T1CN.1) is logic 0, the timer’s input clock is a function of the system clock. When C/T1 = 1, pulses on the T1 pin arecounted. Counti

8.1.3 Timer 1 Mode: Up/Down Count with Auto-ReloadThe up/down count auto-reload option is enabled by the DCEN (T1CN.4) bit. When DCEN is set to logic

(T1CN.2) must also be set to logic 1 to enable the timer. The DCEN bit has no effect in this mode. This mode produces a 50% dutycycle square-wave outp

8-6MAXQ Family User’s Guide8.2.2 Timer/Counter 1 High Register (T1H)Bits 7 to 0: Timer/Counter 1 High (T1H.[7:0]). The T1H register is used to load th

8.2.6 Timer/Counter 1 Mode Register (T1MD)Bits 7 to 2: ReservedBit 1: Enable Timer 1 Interrupt (ET1). Setting this bit to 1 enables interrupts from th

9-1MAXQ Family User’s GuideSECTION 9: TIMER/COUNTER 2 MODULEThis section contains the following information:9.1 Timer 2 . . . . . . . . . . . . . . .

2-3MAXQ Family User’s GuideSECTION 2: ARCHITECTUREThe MAXQ architecture is designed to be modular and expandable. Top-level instruction decoding is ex

9.3.2 Measure High-Pulse Duration Repeatedly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-119.3.3 Measure Period . . . .

9-3MAXQ Family User’s GuideLIST OF FIGURESLIST OF TABLESFigure 9-1. Timer 2 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-4MAXQ Family User’s GuideSECTION 9: TIMER/COUNTER 2 MODULEThe Timer/Counter 2 Module provides a 16-bit programmable timer/counter with pulse-width m

9-5MAXQ Family User’s Guide9.2 Modes of OperationAs summarized in Table 9-1, Timer 2 can provide six timer functions. The Timer 2 operating mode selec

9-6MAXQ Family User’s Guide9.2.1 16-Bit Timer: Auto-Reload/CompareThe 16-bit auto-reload/compare mode for Timer 2 is in effect when the Timer 2 mode s

9-7MAXQ Family User’s Guide9.2.1.5 Capture/Reload ControlFor the 16-bit compare operating mode, the CPRL2 bit is not used. 9.2.2 16-Bit Timer: Capture

9-8MAXQ Family User’s Guide9.2.3.1 Output EnableFor Timer 2 to serve as a counter, the T2P pin must be used as an input. Thus, when C/T2 = 1, the T2OE

9-9MAXQ Family User’s Guide9.2.5 8-Bit Timer/8-Bit Capture ModeWhen the CCF[1:0] bits are configured to a state other than 00b, the edge-capture mode

9-10MAXQ Family User’s Guide9.3 Timer 2 Capture Application ExamplesThe following examples and accompanying figures (Figures 9-4 through 9-8) are used

9-11MAXQ Family User’s Guide9.3.2 Measure High-Pulse Duration RepeatedlyTo measure the duration of high pulses seen on the T2P input pin repeatedly, T

2-4MAXQ Family User’s GuideMemory access from the MAXQ is based on a Harvard architecture with separate address spaces for program and data memory. Th

9-12MAXQ Family User’s Guide9.3.3 Measure Period To measure the period of the signal seen on the T2P input pin, Timer 2 could be configured for a sing

9-13MAXQ Family User’s Guide9.3.4 Measure Duty Cycle RepeatedlyTo measure the duty cycle of the signal seen on the T2P input pin, Timer 2 could be con

9-14MAXQ Family User’s Guide9.3.5 Overflow/Interrupt on Cumulative TimeTo cause an overflow only when the T2P pin has been low for some cumulative dur

9-15MAXQ Family User’s Guide9.4 Timer/Counter 2 Peripheral Registers9.4.1 Timer/Counter 2 Configuration Register (T2CFG)Bit 7: Timer 2 Clock Input Sel

9-16MAXQ Family User’s Guide9.4.2 Timer/Counter 2 Control Register A (T2CNA)Bit 7: Enable Timer 2 Interrupts (ET2). This bit serves as the local enabl

9-17MAXQ Family User’s GuideCompare Mode:If SS2 is written to 1 while in compare mode, one cycle of the defined waveform (reload to overflow) is outpu

9-18MAXQ Family User’s Guide9.4.4 Timer 2 Value Register (T2V)Bits 15 to 0: Timer 2 Value (T2V.[15:0]). The T2V register is a 16-bit register that hol

9-19MAXQ Family User’s Guide9.4.7 Timer 2 Reload High Register (T2RH)Bits 7 to 0: Timer 2 Reload High (T2RH.[7:0]). This register is used to load and

9-20MAXQ Family User’s Guide9.5 Low-Speed Infrared Transmit/Receive Support Using Timer 2The MAXQ microcontroller can provide hardware to simplify sup

9-21MAXQ Family User’s Guide9.5.2.1 IR Encoding (Transmit) ExampleFor any encoding scheme, the proper T2L subcarrier generation settings should be est