Maxim-integrated MAXQ Family Users Guide: MAXQ2010 Supplement User Manual

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MAXQ Family User’s Guide: MAXQ2010 SupplementxLIST OF TABLESTable 2-1. System Clock Generation and Control Registers. . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement20-820.7 LCD Internal Adjustable Contrast ResistorFor an LCD segment to be in the off state, the VRMS vol

MAXQ Family User’s Guide: MAXQ2010 Supplement20-920.8 LCD Frame FrequencyThe LCD controller clock frequency (fLCD) can be sourced from either the 32kH

MAXQ Family User’s Guide: MAXQ2010 Supplement20-1020.9 LCD Display MemoryThe LCD0 to LCD20 registers provide 21 bytes of display memory. Depending on

MAXQ Family User’s Guide: MAXQ2010 Supplement20-11Table 20-4. LCD Display Memory Map (1/2 Duty)Table 20-5. LCD Display Memory Map (1/3 Duty)REGISTERBI

MAXQ Family User’s Guide: MAXQ2010 Supplement20-1220.10 Display Waveform GenerationOnce the operational modes and display memory registers on the LCD

MAXQ Family User’s Guide: MAXQ2010 Supplement20-13In x4 multiplexed mode, also known as 1/4 duty cycle mode, each segment pin can drive up to four LCD

MAXQ Family User’s Guide: MAXQ2010 Supplement20-14According to the static memory map table, a value of 0F6h should be written to the LCD0 register as

MAXQ Family User’s Guide: MAXQ2010 Supplement20-1520.12 LCD Controller 1/2 Duty Cycle Drive ExampleIn this example, SEG0 to SEG3 are used to drive t

MAXQ Family User’s Guide: MAXQ2010 Supplement20-16Figure 20-8. 1/2 Duty Drive Example Waveform TimingFigure 20-9. 1/3 Drive Example Display Connection

MAXQ Family User’s Guide: MAXQ2010 Supplement20-17Table 20-11. 1/3 Duty Drive Example Common Signal SelectionTable 20-12. 1/3 Duty Drive Example Regis

MAXQ Family User’s Guide: MAXQ2010 SupplementxiTable 20-13. 1/4 Duty Drive Example Common Signal Selection . . . . . . . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement20-1820.14 LCD Controller 1/4 Duty Cycle Drive ExampleIn this example, SEG0 and SEG1 are used to drive th

MAXQ Family User’s Guide: MAXQ2010 Supplement20-1920.15 LCD Controller Example: Initializing the LCD Controller move LCRA, #03E0h ; LCRA.FRM = 7 Set

MAXQ Family User’s Guide: MAXQ2010 Supplement21-1SECTION 21: TIMER/COUNTER B MODULE (SPECIFIC TO MAXQ2010)The MAXQ2010 provides three Type B timer/cou

MAXQ Family User’s Guide: MAXQ2010 Supplement21-221.1 Timer/Counter B Register DescriptionsThe following peripheral registers are used to control the

MAXQ Family User’s Guide: MAXQ2010 Supplement21-321.1.3 Timer B Timer/Counter 0/1/2 Control Register (TB0CN, TB1CN, TB2CN; M4[08h], M4[0Ah], M4[0Ch])B

MAXQ Family User’s Guide: MAXQ2010 Supplement21-4Bit 5: Timer B Output Enable (TBOE). Setting this bit to 1 enables the clock output function on the T

MAXQ Family User’s Guide: MAXQ2010 Supplement21-521.2 Timer/Counter B OperationTimer/Counter B is a 16-bit programmable device that supports clock inp

MAXQ Family User’s Guide: MAXQ2010 Supplement21-621.2.2 Timer B 16-Bit Capture ModeThe 16-bit capture mode of Timer B is configured by setting the CP/

MAXQ Family User’s Guide: MAXQ2010 Supplement21-721.2.3 Timer B 16-Bit Up/Down Count with Autoreload ModeThe 16-bit up/down-count autoreload mode is e

MAXQ Family User’s Guide: MAXQ2010 Supplement21-821.2.4 Timer B Clock Output ModeTimer B can be configured to drive a clock output on the TBA pin as s

MAXQ Family User’s Guide: MAXQ2010 Supplement1-1ADDENDUM TO SECTION 1: OVERVIEWThis document is provided as a supplement to the MAXQ Family Use

MAXQ Family User’s Guide: MAXQ2010 Supplement21-9When the timer is not running (i.e., TRB = 0), the initial output state of the TBB pin

MAXQ Family User’s Guide: MAXQ2010 Supplement21-1021.2.7 16-Bit Up/Down Count PWM/Output Control ModeFigure 21-7 shows a functional diagram of th

MAXQ Family User’s Guide: MAXQ2010 Supplement21-11Figure 21-7. Timer B Up/Down-Count PWM/Output Control Mode Block DiagramFigure 21-8. Timer B PWM/Out

MAXQ Family User’s Guide: MAXQ2010 Supplement21-1221.2.8 EXENB Control During PWM/Output Control ModeThe TBB input function (EXENB = 1) and the PWM/ou

MAXQ Family User’s Guide: MAXQ2010 Supplement22-1SECTION 22 : I2C BUS INTERFACE (SPECIFIC TO MAXQ2010)The MAXQ2010 provides an inter-IC (I2C) communic

MAXQ Family User’s Guide: MAXQ2010 Supplement22-222.1.1.1 I2C Data Read and WriteData for I2C transfer is read and written to this location. The I2C t

MAXQ Family User’s Guide: MAXQ2010 Supplement22-3Bit 4: I2C Timeout Interrupt Flag (I2CTOI). This bit is set to 1 if either the I2C controller cannot

MAXQ Family User’s Guide: MAXQ2010 Supplement22-4Stretch Interrupt Enable (I2CSTRIE). Setting this bit to 1 generates an interrupt to the CPU when the

MAXQ Family User’s Guide: MAXQ2010 Supplement22-5Note that this bit has no effect when the I2C is operating in slave mode (I2CMST = 0) and is reset to

MAXQ Family User’s Guide: MAXQ2010 Supplement22-6Bits 7:0: I2C Clock Low (I2CCKL[7:0]). These bits define the I2C SCL low period in number of system c

MAXQ Family User’s Guide: MAXQ2010 Supplement2-1ADDENDUM TO SECTION 2: ARCHITECTUREThe MAXQ2010 shares the common architecture features with oth

MAXQ Family User’s Guide: MAXQ2010 Supplement22-722.2 I2C Code Examples22.2.1 I2C Example 1: Master Mode Transmit; I2C configured as master, transmit

MAXQ Family User’s Guide: MAXQ2010 Supplement22-822.2.3 I2C Example 3: Slave Mode Receive; I2C configured as slave with address 1ah; Setup for Slave M

MAXQ Family User’s Guide: MAXQ2010 Supplement23-1SECTION 23: SUPPLY VOLTAGE MONITOR AND POWER CONTROL (SPECIFIC TO MAXQ2010)The MAXQ2010 provides a nu

MAXQ Family User’s Guide: MAXQ2010 Supplement23-2Bits 14:10: ReservedBits 9:8: 32kHz Oscillator Mode (32KMD[1:0]). These two bits determine the

MAXQ Family User’s Guide: MAXQ2010 Supplement23-323.1.2 Supply Voltage Monitor Register (SVM, M1[0Dh])Bits 15:12, 7:5: ReservedBits 11:8: Supply Volta

MAXQ Family User’s Guide: MAXQ2010 Supplement24-1SECTION 24: UTILITY ROM (SPECIFIC TO MAXQ2010)24.1 OverviewThe MAXQ2010 utility ROM includes routines

MAXQ Family User’s Guide: MAXQ2010 Supplement24-224.2 In-Application Programming Functions24.2.1 UROM_flashWriteNotes:• This function uses one stack

MAXQ Family User’s Guide: MAXQ2010 Supplement24-324.3 Data Transfer FunctionsThe following utility ROM functions are used to transfer data from one me

MAXQ Family User’s Guide: MAXQ2010 Supplement24-424.3.1 UROM_moveDP0Notes:• Before calling this function, DPC should be set appropriately to configur

MAXQ Family User’s Guide: MAXQ2010 Supplement24-524.3.4 UROM_moveDP1Notes:• Before calling this function, DPC should be set appropriately to configur

MAXQ Family User’s Guide: MAXQ2010 Supplement2-2Figure 2-1. MAXQ2010 System and Peripheral Register MapOOhMCNTO1hO2hO3hO4hO5hO6hO7hO8hO9h10h11hREGISTE

MAXQ Family User’s Guide: MAXQ2010 Supplement24-624.3.7 UROM_moveBPNotes:• Before calling this function, DPC should be set appropriately to configure

MAXQ Family User’s Guide: MAXQ2010 Supplement24-724.3.10 UROM_copyBufferNotes:• This function can be used to copy from program flash to data RAM, or

MAXQ Family User’s Guide: MAXQ2010 Supplement24-824.4.2 Utility ROM Example 2: Reading Constant Byte Data from Flash (Indirect Function Call) move D

MAXQ Family User’s Guide: MAXQ2010 SupplementA1-1APPENDIX 1: SAMPLE MAXQ2010 DEVICE INCLUDE FILE FOR MAX-IDE#define PO0 M0[00h] ; Port 0 Output#defi

MAXQ Family User’s Guide: MAXQ2010 SupplementA1-2#define EIES1 M1[0Bh] ; External Interrupt Edge Select 1#define EIES2 M1[0Ch] ; External Interrup

MAXQ Family User’s Guide: MAXQ2010 SupplementA1-3#define I2CBUF M3[00h] ; I2C Data Buffer#define I2CST M3[01h] ; I2C Status#define I2CIE M3[02h]

MAXQ Family User’s Guide: MAXQ2010 SupplementA1-4INDX_moveDP1inc equ 7INDX_moveDP1dec equ 8INDX_moveBP equ 9INDX_moveBPinc equ 10INDX_moveBPde

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

MAXQ Family User’s Guide: MAXQ2010 Supplement2-32.4 Memory OrganizationAs with all MAXQ microcontrollers, the MAXQ2010 contains logically separate pro

MAXQ Family User’s Guide: MAXQ2010 Supplement2-4Figure 2-2. Memory Map When Executing from Program Flash MemoryFigure 2-3. Memory Map When Executing f

MAXQ Family User’s Guide: MAXQ2010 Supplement2-52.6 Clock GenerationAll functional modules in the MAXQ2010 are synchronized to a single system clock.

MAXQ Family User’s Guide: MAXQ2010 Supplement2-62.6.2 External 32kHz Crystal Oscillator CircuitThe 32kHz oscillator operates as described in Section 2

MAXQ Family User’s Guide: MAXQ2010 Supplement2-7Table 2-1. System Clock Generation and Control Registers2.6.3 Frequency-Locked Loop (FLL)The MAXQ2010

MAXQ Family User’s Guide: MAXQ2010 SupplementiiTABLE OF CONTENTSADDENDUM TO SECTION 1: OVERVIEW 1-11.1 References. . . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement2-8When the system clock source is switched back from the FLL to the high-frequency oscillator by cleari

MAXQ Family User’s Guide: MAXQ2010 Supplement2-92.8 Reset ConditionsThere are four possible reset sources for the MAXQ2010. While in the reset state,

MAXQ Family User’s Guide: MAXQ2010 Supplement2-102.8.1 Power-On ResetWhen power is first applied to the MAXQ2010, or when the supply voltage at VD

MAXQ Family User’s Guide: MAXQ2010 Supplement2-11Figure 2-7. External Reset TimingTable 2-3. System Power-Management RegistersCLOCKRSTRESET SAMPLINGIN

MAXQ Family User’s Guide: MAXQ2010 Supplement2-122.9.1 Divide-by-256 Mode (PMM)In this power-management mode, all operations continue as normal, but a

MAXQ Family User’s Guide: MAXQ2010 Supplement2-13• An ADC conversion is initiated by setting ADCONV to 1.• Active debug mode is entered either by a

MAXQ Family User’s Guide: MAXQ2010 Supplement3-1ADDENDUM TO SECTION 3: PROGRAMMINGRefer to Section 3: Programming of the MAXQ Family User’s Guide for

MAXQ Family User’s Guide: MAXQ2010 Supplement4-1ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONSRefer to Section 4: System Register Descriptions of

MAXQ Family User’s Guide: MAXQ2010 Supplement4-2Table 4-2. System Register Bit Functions (continued)Table 4-3. System Register Reset ValuesNote: Bits

MAXQ Family User’s Guide: MAXQ2010 Supplement4-34.1 System Register DescriptionsThis section details the functionality of any system register containe

MAXQ Family User’s Guide: MAXQ2010 Supplementiii6.1.2 Port 1 Direction Register (PD1, M0[11h]) . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement4-44.1.3 System Control Register (SC, M8[08h])Bit 7: Test Access (Debug) Port Enable (TAP)0 = Debug port

MAXQ Family User’s Guide: MAXQ2010 Supplement4-54.1.5 System Clock Control Register (CKCN, M8[0Eh])The CKCN register bit settings determine the system

MAXQ Family User’s Guide: MAXQ2010 Supplement4-6Table 4-4. System Clock ModesFLLMD SWB PMME CD1 CD0 SYSTEM CLOCK SWITCHBACK0 0 0 0 0 High-frequency cl

MAXQ Family User’s Guide: MAXQ2010 Supplement5-1ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULESTable 5-1. Peripheral Register MapNote: Register nam

MAXQ Family User’s Guide: MAXQ2010 Supplement5-2Table 5-2. Peripheral Register Bit FunctionsREGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0PO0 PO0 (8 bits

MAXQ Family User’s Guide: MAXQ2010 Supplement5-3Table 5-2. Peripheral Register Bit Functions (continued)REGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0SPI

MAXQ Family User’s Guide: MAXQ2010 Supplement5-4Table 5-2. Peripheral Register Bit Functions (continued)Table 5-3. Peripheral Register Bit Reset Value

MAXQ Family User’s Guide: MAXQ2010 Supplement5-5Table 5-3. Peripheral Register Bit Reset Values (continued)REGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAXQ Family User’s Guide: MAXQ2010 Supplement5-6Table 5-3. Peripheral Register Bit Reset Values (continued)Note: Bits marked as “s” have special behav

MAXQ Family User’s Guide: MAXQ2010 Supplement6-1ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULEThe MAXQ2010 provides up to 55 port pins for general-

MAXQ Family User’s Guide: MAXQ2010 SupplementivADDENDUM TO SECTION 10: SERIAL I/O MODULE 10-110.1 Serial USART I/O Pins and Control Registers . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement6-2Table 6-1. Port Pin Special and Alternate Functions (continued)PORT PIN FUNCTION TYPE FUNCTION ENABLED

MAXQ Family User’s Guide: MAXQ2010 Supplement6-3Table 6-1. Port Pin Special and Alternate Functions (continued)PORT PIN FUNCTION TYPE FUNCTION ENABLED

MAXQ Family User’s Guide: MAXQ2010 Supplement6-4The port pins on the MAXQ2010 operate the same as standard MAXQ port pins, with input/output states de

MAXQ Family User’s Guide: MAXQ2010 Supplement6-56.1.3 Port 2 Direction Register (PD2, M0[12h])Each of the bits in this register controls the input/out

MAXQ Family User’s Guide: MAXQ2010 Supplement6-66.1.6 Port 5 Direction Register (PD5, M1[11h])Each of the bits in this register controls the input/out

MAXQ Family User’s Guide: MAXQ2010 Supplement6-76.1.10 Port 2 Output Register (PO2, M0[02h])Bits 7:0: Port 2 Output. This register stores the data tha

MAXQ Family User’s Guide: MAXQ2010 Supplement6-86.1.14 Port 6 Output Register (PO6, M1[02h])Bits 7:0: Port 6 Output. This register stores the data tha

MAXQ Family User’s Guide: MAXQ2010 Supplement6-96.1.18 Port 3 Input Register (PI3, M0[0Bh])Each of the read-only bits in this register reflects the lo

MAXQ Family User’s Guide: MAXQ2010 Supplement6-106.1.22 External Interrupt Flag 0 Register (EIF0, M0[04h])Each bit in this register is set when a nega

MAXQ Family User’s Guide: MAXQ2010 Supplement6-116.1.24 External Interrupt Flag 2 Register (EIF2, M1[06h])Each bit in this register is set when a nega

MAXQ Family User’s Guide: MAXQ2010 SupplementvADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) 17-117.1 JTAG Bootloader Protocol . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement6-126.1.26 External Interrupt Enable 1 Register (EIE1, M1[05h])Each bit in this register controls the ena

MAXQ Family User’s Guide: MAXQ2010 Supplement6-136.1.28 External Interrupt Edge Select 0 Register (EIES0, M0[0Ch])Each bit in this register controls t

MAXQ Family User’s Guide: MAXQ2010 Supplement6-146.1.30 External Interrupt Edge Select 2 Register (EIES2, M1[0Ch])Each bit in this register controls t

MAXQ Family User’s Guide: MAXQ2010 Supplement6-156.2.3 External Interrupt Example: Handling Interrupt on INT10/P5.2 move PD5.2, #0 ; Set P5.2 to

MAXQ Family User’s Guide: MAXQ2010 Supplement7-1ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULEThe MAXQ2010 does not provide this peripheral module.

MAXQ Family User’s Guide: MAXQ2010 Supplement8-1ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULEThe MAXQ2010 does not provide this peripheral module.

MAXQ Family User’s Guide: MAXQ2010 Supplement9-1ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULEThe MAXQ2010 does not provide this peripheral module.

MAXQ Family User’s Guide: MAXQ2010 Supplement10-1ADDENDUM TO SECTION 10: SERIAL I/O MODULEThe MAXQ2010 provides two serial universal synchronous

MAXQ Family User’s Guide: MAXQ2010 Supplement10-2mainLoop: call RxChar0 call TxChar0 jump mainLoop;================================================

MAXQ Family User’s Guide: MAXQ2010 Supplement11-1ADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULEThe MAXQ2010 provides a serial periph

MAXQ Family User’s Guide: MAXQ2010 Supplementvi20.2.13 LCD Display Register 10 (LCD10, M2[15h]) . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement11-211.2.2 SPI Example 2: Receiving Data in Slave Mode move SPICN, #01h ; Enable SPI in slave mode mov

MAXQ Family User’s Guide: MAXQ2010 Supplement12-1ADDENDUM TO SECTION 12: HARDWARE MULTIPLIER MODULEThe MAXQ2010 provides a hardware multiplier m

MAXQ Family User’s Guide: MAXQ2010 Supplement13-1ADDENDUM TO SECTION 13: 1-Wire BUS MASTERThe MAXQ2010 does not provide this peripheral module.

MAXQ Family User’s Guide: MAXQ2010 Supplement14-1ADDENDUM TO SECTION 14: REAL-TIME CLOCK MODULEThe MAXQ2010 provides a real-time clock (RTC) th

MAXQ Family User’s Guide: MAXQ2010 Supplement14-214.3 RTC Trim OperationThe uncompensated accuracy of the RTC is a function of the attached crystal os

MAXQ Family User’s Guide: MAXQ2010 Supplement14-3Figure 14-2. RTC Prescaler and TrimFigure 14-3. RTC Trim Adjustment (TSGN = 1)Figure 14-4. RTC Trim A

MAXQ Family User’s Guide: MAXQ2010 Supplement14-414.4 RTC Register DescriptionsAddresses of registers are given as “Mx[yy],” where x is the module num

MAXQ Family User’s Guide: MAXQ2010 Supplement14-5Bit 15: RTC Write Enable (WE). This register bit serves as a protection mechanism against undesirable

MAXQ Family User’s Guide: MAXQ2010 Supplement14-614.4.3 Real-Time Subsecond Counter Register (RTSS, M0[1Ah])Bits 7:0: RTC Subsecond Counter Register.

MAXQ Family User’s Guide: MAXQ2010 Supplement14-714.4.6 RTC Subsecond Alarm Register (RSSA, M0[1Dh])Bits 7:0: RTC Subsecond Alarm Register. This regis

MAXQ Family User’s Guide: MAXQ2010 Supplementvii21.2.7 16-Bit Up/Down Count PWM/Output Control Mode . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement14-814.5 RTC Example: Starting and Setting the Clock move RCNT, #08000h ;RTC write enable call wait_bu

MAXQ Family User’s Guide: MAXQ2010 Supplement15-1ADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP)The JTAG/TAP port on the MAXQ2010 is multiplexed with p

MAXQ Family User’s Guide: MAXQ2010 Supplement16-1ADDENDUM TO SECTION 16: IN-CIRCUIT DEBUG MODEThe MAXQ2010 provides an in-circuit debugging interface

MAXQ Family User’s Guide: MAXQ2010 Supplement16-2• Registers SPIB, I2CBUF, and ADDATA are not read, and their values are returned as 0000h.The first

MAXQ Family User’s Guide: MAXQ2010 Supplement17-1ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG)The MAXQ2010 provides a JTAG-compatible debug por

MAXQ Family User’s Guide: MAXQ2010 Supplement17-217.2 Family 0 Commands (Not Password Protected)Command 00h—No OperationCommand 01h—Exit LoaderThis co

MAXQ Family User’s Guide: MAXQ2010 Supplement17-3Command 05h—Get Supported CommandsThe SupportL (LSB) and SupportH (MSB) bytes form a 16-bit value tha

MAXQ Family User’s Guide: MAXQ2010 Supplement17-4Command 08h—Get Loader VersionCommand 09h—Get Utility ROM VersionCommand 0Ah—Set Word/Byte-Mode Acces

MAXQ Family User’s Guide: MAXQ2010 Supplement17-5Command 11h—Load Data Variable LengthThis command writes (Length) bytes of data into the data SRAM st

MAXQ Family User’s Guide: MAXQ2010 Supplement17-617.5 Family 3 Commands: CRC Variable Length (Password Protected)Command 30h—CRC Code Variable LengthT

MAXQ Family User’s Guide: MAXQ2010 Supplementviii24.3.6 UROM_moveDP1dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement17-717.7 Family 5 Commands: Load and Verify Variable Length (Password Protected)Command 50h—Load and Veri

MAXQ Family User’s Guide: MAXQ2010 Supplement18-1ADDENDUM TO SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARYRefer to the MAXQ Family User’s Guide. Tab

MAXQ Family User’s Guide: MAXQ2010 Supplement18-2Note 1: The active accumulator (Acc) is not allowed as the src in operations where it is the implici

MAXQ Family User’s Guide: MAXQ2010 Supplement19-1SECTION 19: ANALOG-TO-DIGITAL CONVERTER (SPECIFIC TO MAXQ2010)The MAXQ2010 provides a 12-bit, su

MAXQ Family User’s Guide: MAXQ2010 Supplement19-219.2 Analog-to-Digital Pins and Control RegistersTables 19-1 and 19-2 list the pins and control regis

MAXQ Family User’s Guide: MAXQ2010 Supplement19-3The following peripheral registers are used to control the analog-to-digital converter functions.19.2

MAXQ Family User’s Guide: MAXQ2010 Supplement19-4Bit 7: Internal Reference OK (REFOK). This read-only status bit indicates whether the internal refere

MAXQ Family User’s Guide: MAXQ2010 Supplement19-519.2.2 ADC Conversion Sequence Address Register (ADADDR, M4[07h])Bits 15:12, 7, 3: ReservedBits 11:8

MAXQ Family User’s Guide: MAXQ2010 Supplement19-6Bits 9:8: ADC Clock Divider (ADCLK[1:0]). These bits control the generation of the ADC clock from the

MAXQ Family User’s Guide: MAXQ2010 Supplement19-7Bits 3:0: ADC Sample Acquisition Time Extend (ADACQ[3:0]). These bits set the extended sample acquisi

MAXQ Family User’s Guide: MAXQ2010 SupplementixLIST OF FIGURESFigure 2-1. MAXQ2010 System and Peripheral Register Map . . . . . . . . . . . . . . . .

MAXQ Family User’s Guide: MAXQ2010 Supplement19-819.2.6 ADC Conversion Configuration Registers (ADCFG[0] to ADCFG[7], ADDATA[10h] to ADDATA[17h])The e

MAXQ Family User’s Guide: MAXQ2010 Supplement19-919.3 Analog-to-Digital Converter Code Examples19.3.1 ADC Example 1: Single Conversion move ADCN, #

MAXQ Family User’s Guide: MAXQ2010 Supplement19-10 move A[6], ADDATA move A[7], ADDATA move A[8], ADDATA move A[9], ADDATA move A[10], A

MAXQ Family User’s Guide: MAXQ2010 Supplement20-1SECTION 20: LCD CONTROLLER (SPECIFIC TO MAXQ2010)20.1 LCD Controller OverviewThe MAXQ2010 provides an

MAXQ Family User’s Guide: MAXQ2010 Supplement20-220.2 LCD Controller Register DescriptionsThe following peripheral registers are used to control the L

MAXQ Family User’s Guide: MAXQ2010 Supplement20-3Bit 1: Operation Mode (OPM). This bit determines whether the LCD controller is operating (driving

MAXQ Family User’s Guide: MAXQ2010 Supplement20-4Bits 3:0: LCD Register Adjust (LRA[3:0]). These bits control the resistance of the internal LCD resis

MAXQ Family User’s Guide: MAXQ2010 Supplement20-520.2.9 LCD Display Register 6 (LCD6, M2[11h])20.2.10 LCD Display Register 7 (LCD7, M2[12h])20.2.11 LC

MAXQ Family User’s Guide: MAXQ2010 Supplement20-620.2.15 LCD Display Register 12 (LCD12, M2[17h])20.2.16 LCD Display Register 13 (LCD13, M2[18h])20.2.

MAXQ Family User’s Guide: MAXQ2010 Supplement20-720.2.21 LCD Display Register 18 (LCD18, M2[1Dh])20.2.22 LCD Display Register 19 (LCD19, M2[1Eh])20.2.