Maxim-integrated Ultra-High-Speed Flash Microcontroller User Manual Page 36
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Ultra-High-Speed Flash
Microcontroller User’s Guide
SADEN1.7–0
Bits 7–0
Slave Address Mask Enable Register 1. This register functions as a mask when comparing ser-
ial port 1 addresses for automatic address recognition. When a bit in this register is set, the corre-
sponding bit location in the SADDR1 register is exactly compared with the incoming serial port 1
data to determine if a receiver interrupt should be generated. When a bit in this register is cleared,
the corresponding bit in the SADDR1 register becomes a “don’t care” and is not compared against
the incoming data. All incoming data generates a receiver interrupt when this register is cleared.
SM0–2
Bits 7, 6, 5
Serial Port 1 Mode. These bits control the mode of serial port 1 as shown in the following table. In
addition, the SM0 and SM2 bits have secondary functions as shown.
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Serial Port 1 Control (SCON1)
76543210
SFR C0h SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Table 4-15. Serial Port 1 Modes and Functions
SM0 SM1 SM2 MO DE FU N CTION LENG TH (BITS) PERIOD
0 0 0 0 Synchronous 8 See P MR reg ister
0 0 1 0 Synchronous 8 See P MR reg ister
0 1 X 1 Asynchronous 10 Timer 1 or 2 baud rate equation
1 0 0 2 As ynchronous 11 See P MR reg ister
1 0 1 2
Asynchronous w ith mult i processor
communication
11 See PMR register
1 1 0 3 As ynchronous 11 Ti mer 1 or 2 baud rate equation
1 1 1 3
Asynchronous w ith mult i processor
communication
11 Timer 1 or 2 baud rate equation
SM0/FE_1
Bit 7
SM1_1
Bit 6
Framing Error Flag. When SMOD0 (PCON.6) = 0, this bit is used as a mode select bit (SM0) for
serial port 1. When SMOD0 (PCON.6) = 1, this bit becomes a framing error (FE) bit, which reports
detection of an invalid stop bit. When used as FE, this bit must be cleared in software. Once the
SMOD0 bit is set, modifications to this bit do not affect the serial port mode settings. Although
accessed from the same register, the data for bits SM0 and FE are stored internally in different
physical locations.
No Alternate Function.
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Slave Address Mask Enable Register 1 (SADEN1)
7 6 5 4 3 2 1 0
SFR BAh SADE N1.7 SADE N1.6 SADE N1.5 SADE N1.4 SADE N1.3 SADE N1.2 SADE N1.1 SADE N1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Maxim Integrated
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