Maxim-integrated DS33R11 manuals

Maxim integrated DS33R11 User Manual (344 pages)

Brand: Maxim-integrated | Category: Computer Accessories | Size: 11.08 MB |

English

Table of contents

T1/E1/J1 Transceive

1

TABLE OF CONTENTS

2

LIST OF FIGURES

6

LIST OF TABLES

8

1 DESCRIPTION

9

2 FEATURE HIGHLIGHTS

11

2.7 SDRAM Interface

12

2.8 MAC Interface

12

2.9 T1/E1/J1 Line Interface

13

2.10 Clock Synthesizer

13

2.11 Jitter Attenuator

13

2.12 T1/E1/J1 Framer

14

2.13 TDM Bus

14

2.14 Test and Diagnostics

15

3 APPLICATIONS

17

4 ACRONYMS AND GLOSSARY

18

5 MAJOR OPERATING MODES

19

6 BLOCK DIAGRAMS

20

FRAMER BACKPLANE

21

INTERFACE

21

32.768MHz

22

24 of 344

24

7 PIN DESCRIPTIONS

25

8 FUNCTIONAL DESCRIPTION

41

8.1 Processor Interface

42

9 ETHERNET MAPPER

43

ETHERNET

44

T1/E1/J1

44

TRANSCEIVER

44

Table 9-2. Reset Functions

46

9.4 Global Resources

47

9.5 Per-Port Resources

47

9.6 Device Interrupts

48

9.8 Status Registers

50

9.9 Information Registers

50

9.10 Serial Interface

50

9.11 Connections and Queues

51

9.12 Arbiter

52

9.13 Flow Control

53

9.14.1 DTE and DCE Mode

58

9.15 Ethernet MAC

59

Figure 9-7. RMII Interface

61

BERT Features

62

LoadVerify

63

MatchVerify

64

802.3 MAC Frame

68

Rate Adaption

68

10.2 Per-Channel Operation

73

10.6 Per-Channel Loopback

77

10.7 Error Counters

78

SIGNALING

82

EXTRACTION

82

10.12.4 Minimum Delay Mode

89

NEW Sa BIT

90

TPOSO/TNEGO

90

10.14.1 Transmit BOC

91

10.14.2 Receive BOC

91

10.16.1 HDLC Configuration

93

10.16.2 FIFO Control

95

10.16.3 HDLC Mapping

95

10.16.4 FIFO Information

96

10.17.1 Overview

97

10.17.2 Receive Section

97

10.18 D4/SLC-96 Operation

98

10.20.1 LIU Operation

100

10.20.2 Receiver

100

10.20.3 Transmitter

102

01 11001

103

10.24 Recommended Circuits

104

Figure 10-7. Basic Interface

104

LEVEL AS PER

106

TOLERANCE

106

MINIMUM TOLERANCE

106

JITTER ATTENUATION (dB)

107

10.25.1 BERT Status

108

10.25.2 BERT Mapping

108

10.25.4 BERT Bit Counter

110

10.25.5 BERT Error Counter

110

T1 TRANSMIT

113

114 of 344

114

E1 TRANSMIT

115

To Bipolar/NRZ

116

11 DEVICE REGISTERS

117

11.1 Register Bit Maps

118

SAPINE01IM SAPINEFEIM

121

11.1.6 MAC Register Bit Map

123

11.3 Arbiter Registers

143

11.4 BERT Registers

144

0 = interrupt disabled

148

11.5.2 X.86 Registers

159

11.6.2 MAC Registers

186

12 FUNCTIONAL TIMING

300

TXD[3:0]

301

P R E A E M B L E

301

TXD[1:0]

302

P R E A M B L E F C S

302

123456789101112

306

13141516171819202122232412345

306

CHANNEL 1CHANNEL 32

307

CHANNEL 31

307

12.4 E1 Mode

308

Enabled)

311

13 OPERATING PARAMETERS

313

13.2 MII Interface

315

10Mbps 100Mbps

316

PARAMETER SYMBOL

316

MIN TYP MAX MIN TYP MAX

316

13.3 RMII Interface

317

13.4 MDIO Interface

319

Table 13-9. MDIO Interface

319

13.5 Transmit WAN Interface

320

13.6 Receive WAN Interface

321

13.7 SDRAM Timing

322

Address Valid

325

Data Valid

325

RSYSCLK = 1.544MHz

327

RSYSCLK = 2.048MHz

327

1ST FRAME BIT

328

13.12 JTAG Interface Timing

335

14 JTAG INFORMATION

336

14.2 Instruction Register

339

14.3 JTAG ID Codes

341

14.4 Test Registers

341

14.5 JTAG Functional Timing

342

15 PACKAGE INFORMATION

343

16 DOCUMENT REVISION HISTORY

344

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