Simplifying System IntegrationTM 73M1822/73M1922 Implementer’s Guide August 27, 2009 Rev. 1.0 UG_1x22

73M1822/73M1922 Implementer’s Guide UG_1x22_052 10 Rev. 1.0 Begin : RESYNC 1. IF CNT1 !=1 goto 8 2. Write CHNGFS = 1 (RG0D = xxxx_1xxx). 3. Wait

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 11 3.2.2 Initial Line State Configuration The default condition of the device is to be on

73M1822/73M1922 Implementer’s Guide UG_1x22_052 12 Rev. 1.0 Initial Line State ConfigurationENAPOL = 1ENSYNL = 1ENFEL = 1OFH = ENDC = ENAC = ENS

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 13 4 On-Hook Procedures The on-hook procedures described in this section include: • CID

73M1822/73M1922 Implementer’s Guide UG_1x22_052 14 Rev. 1.0 4.2 Off-Hook Request The registers used in the off-hook request procedure are: 0x12

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 15 Off-hook RequestRXBST =0EndTHEN =1ENNOM =0TXEN = RXEN = ATEN =1 OFH = 1 If s

73M1822/73M1922 Implementer’s Guide UG_1x22_052 16 Rev. 1.0 4.3 Ring Detection and Line Voltage Reversal When the 73M1922 is in on-hook mode, and

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 17 If the line voltage does not exceed the threshold within the 25 ms period, RGMON become

73M1822/73M1922 Implementer’s Guide UG_1x22_052 18 Rev. 1.0 Begin @ ring_timer expires 1. If (ring_last - ring_first) < 150 ms Polarity Reversa

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 19 4.4 Line-in-use and Loss of Battery Feed When the FXO line is in the on-hook mode, the

73M1822/73M1922 Implementer’s Guide UG_1x22_052 2 Rev. 1.0 © 2009 Teridian Semiconductor Corporation. All

73M1822/73M1922 Implementer’s Guide UG_1x22_052 20 Rev. 1.0 5 Off-Hook Procedures The off-hook procedures described in this section include: • B

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 21 6 Interrupt Processing During the course of operation the 73M1x22 can be expected to g

73M1822/73M1922 Implementer’s Guide UG_1x22_052 22 Rev. 1.0 6.2 DET Interrupt The triggering of the DET interrupt indicates that the device has de

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 23 6.4 RGDT and RGMON Interrupts The triggering of an RGDT or RGMON interrupt indicates t

73M1822/73M1922 Implementer’s Guide UG_1x22_052 24 Rev. 1.0 7 Register Summary Address (hex) Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 25 8 Related Documentation The following 73M1x22 documents are available from Teridian S

73M1822/73M1922 Implementer’s Guide UG_1x22_052 26 Rev. 1.0 Revision History Revision Date Description 1.0 8/27/2009 First publication.

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 3 Table of Contents 1 Introduction ...

73M1822/73M1922 Implementer’s Guide UG_1x22_052 4 Rev. 1.0 1 Introduction This guide describes how to use the 73M1822 and 73M1922 MicroDAA® for vo

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 5 2 Hardware Requirements 2.1 Reset The 73M1x22 can be initialized to a default state by

73M1822/73M1922 Implementer’s Guide UG_1x22_052 6 Rev. 1.0 3 Device Configuration and Initialization 3.1 Host-Side Device (73M1902) Configuration

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 7 3.1.3 MAFE Interface Configuration R/W ADDR 07 06 05 04 03 02 01 00 Write 0x01 DYSEN

73M1822/73M1922 Implementer’s Guide UG_1x22_052 8 Rev. 1.0 3.2 Line-Side Device (73M1912) Configuration The Line-side device setup includes the fo

UG_1x22_052 73M1822/73M1922 Implementer’s Guide Rev. 1.0 9 Barrier SyncSYNL == 1?SLHS == 1?SLEEP = 1Wait 10 msSLEEP = 0EndNoNoNoYesYesYesRestore Re