Maxim-integrated DS33R11 User Manual

DS33R11Ethernet Mapper with IntegratedT1/E1/J1 Transceiverwww.maxim-ic.com GENERAL DESCRIPTION The DS33R11 extends a 10/100 Ethernet LAN seg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10 of 344 The integrated Ethernet Mapper is software compatible with the DS33Z11 Ethern

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 100 of 344 10.20 Line Interface Unit (LIU) The LIU contains three sections: the receiv

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 101 of 344 10.20.2.1 Receive Level Indicator and Threshold Interrupt The device reports

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 102 of 344 10.20.3 Transmitter The transceiver uses a phase-lock loop along with a prec

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 103 of 344 10.21 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 104 of 344 10.24 Recommended Circuits Figure 10-7. Basic Interface

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 105 of 344 Figure 10-8. E1 Transmit Pulse Template 0 -0.1 -0.2 0

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 106 of 344 Figure 10-10. Jitter Tolerance FREQUENCY (Hz)UNIT INT

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 107 of 344 Figure 10-12. Jitter Attenuation (T1 Mode) FREQUE

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 108 of 344 Figure 10-14. Optional Crystal Connections XTALD C1 C2 1.544MH

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 109 of 344 Figure 10-15. Simplified Diagram of BERT in Network Direction

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11 of 344 2 FEATURE HIGHLIGHTS 2.1 General • 256-pin, 27mm BGA package • 1.8V and 3.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 110 of 344 10.25.3 BERT Repetitive Pattern Set These registers must be properly loade

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 111 of 344 10.26 Payload Error-Insertion Function (T1 Mode Only) An error-insertion fu

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 112 of 344 10.27 Programmable Backplane Clock Synthesizer The transceiver contains an

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 113 of 344 10.29 T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Dia

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 114 of 344 B8ZSEncodingBipolar/NRZcodingT1TCR2.7 B8ZSEIOCR1.0 ODF1/2 CLK/FULL CLKCCR1

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 115 of 344 Figure 10-18. E1 Transmit Flow Diagram TSERTSIGHSIE1-4throughPCPRTXESTOREE

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 116 of 344 Per-Channel Loo

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 117 of 344 11 DEVICE REGISTERS Ten address lines are used to address the register space

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 118 of 344 11.1 Register Bit Maps Table 11-2, Table 11-3, Table 11-4, Table 11-5, Tabl

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 119 of 344 11.1.2 Arbiter Register Bit Map Table 11-3. Arbiter Register Bit Map ADDR

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 12 of 344 2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • Tw

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 120 of 344 11.1.4 Serial Interface Register Bit Map Table 11-5. Serial Interface Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 121 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 114h LI.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 122 of 344 11.1.5 Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 123 of 344 11.1.6 MAC Register Bit Map Table 11-7. MAC Indirect Register Bit Map ADDR

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 124 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 112h RES

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 125 of 344 Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0) ADD

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 126 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 h 01Ah T

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 127 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 h 035h T

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 128 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 h 050h T

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 129 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 06Ah TR.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13 of 344 2.9 T1/E1/J1 Line Interface • Requires only a 2.048MHz master clock for bot

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 130 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 085h TR.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 131 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0A0h TR.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 132 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0C1h TR.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 133 of 344 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0DCh TR.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 134 of 344 11.2 Global Register Definitions for Ethernet Mapper Functions contained in

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 135 of 344 Register Name: GL.CR1 Register Description: Global Control Register 1 Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 136 of 344 Register Name: GL.RTCAL Register Description: Global Receive and Transmit S

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 137 of 344 Register Name: GL.LIS Register Description: Global Serial Interface Interrup

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 138 of 344 Register Name: GL.TRQIE Register Description: Global Transmit Receive Queue

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 139 of 344 Register Name: GL.BIS Register Description: Global BERT Interrupt Status Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 14 of 344 2.12 T1/E1/J1 Framer • Fully independent transmit and receive functionality

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 140 of 344 Register Name: GL.C1QPR Register Description: Connection 1 Queue Pointer Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 141 of 344 Register Name: GL.BISTPF Register Description: BIST Pass-Fail Register Addr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 142 of 344 Register Name: GL.SDMODE2 Register Description: Global SDRAM Mode Register 2

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 143 of 344 11.3 Arbiter Registers The Arbiter manages the transport between the Etherne

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 144 of 344 11.4 BERT Registers Register Name: BCR Register Description: BERT Control R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 145 of 344 Register Name: BPCLR Register Description: BERT Pattern Configuration Low R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 146 of 344 Register Name: BSPB0R Register Description: BERT Pattern Byte0 Register R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 147 of 344 Register Name: TEICR Register Description: Transmit Error Insertion Control

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 148 of 344 Register Name: BSRL Register Description: BERT Status Register Latched Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 149 of 344 Register Name: RBECB0R Register Description: Receive Bit Error Count Byte 0

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 15 of 344 2.14 Test and Diagnostics • IEEE 1149.1 support • Programmable on-chip bit

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 150 of 344 Register Name: RBCB1 Register Description: Receive Bit Count Byte 1 Registe

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 151 of 344 11.5 Serial Interface Registers The Serial Interface contains the Serial HD

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 152 of 344 Register Name: LI.LPBK Register Description: Serial Interface Loopback Contr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 153 of 344 Register Name: LI.TIFGC Register Description: Transmit Inter-Frame Gapping C

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 154 of 344 Register Name: LI.TEPHC Register Description: Transmit Errored Packet High C

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 155 of 344 Register Name: LI.TPPSR Register Description: Transmit Packet Processor Stat

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 156 of 344 Register Name: LI.TPCR0 Register Description: Transmit Packet Count Byte 0 R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 157 of 344 Register Name: LI.TBCR0 Register Description: Transmit Byte Count Byte 0

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 158 of 344 Register Name: LI.THPMUU Register Description: Serial Interface Transmit HD

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 159 of 344 11.5.2 X.86 Registers X.86 transmit and common registers are used to control

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 16 of 344 2.15 Specifications Compliance The DS33R11 meets relevant telecommunications

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 160 of 344 Register Name: LI.TRX86SAPIL Register Description: Transmit Receive X.86 S

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 161 of 344 11.5.3 Receive Serial Interface Serial Receive Registers are used to contro

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 162 of 344 Register Name: LI.RMPSCL Register Description: Receive Maximum Packet Size

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 163 of 344 Register Name: LI.RPPSRL Register Description: Receive Packet Processor Stat

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 164 of 344 Register Name: LI.RPPSRIE Register Description: Receive Packet Processor St

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 165 of 344 Register Name: LI.RPCB0 Register Description: Receive Packet Count Byte 0 Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 166 of 344 Register Name: LI.RFPCB0 Register Description: Receive FCS Errored Packet C

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 167 of 344 Register Name: LI.RAPCB0 Register Description: Receive Aborted Packet Count

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 168 of 344 Register Name: LI.RSPCB0 Register Description: Receive Size Violation Packe

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 169 of 344 Register Name: LI.RBC0 Register Description: Receive Byte Count 0 Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 17 of 344 3 APPLICATIONS The DS33R11 is ideal for application areas such as transparent

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 170 of 344 Register Name: LI.RAC0 Register Description: Receive Aborted Byte Count 0 R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 171 of 344 Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDL

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 172 of 344 Register Name: LI.RX86LSIE Register Description: Receive X.86 Interrupt Enab

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 173 of 344 Register Name: LI.TQTIE Register Description: Serial Interface Transmit Queu

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 174 of 344 11.6 Ethernet Interface Registers The Ethernet Interface registers are use

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 175 of 344 Register Name: SU.MACRD1 Register Description: MAC Read Data Byte 1 Registe

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 176 of 344 Register Name: SU.MACWD1 Register Description: MAC Write Data 1 Register Ad

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 177 of 344 Register Name: SU.MACAWH Register Description: MAC Address Write High Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 178 of 344 Register Name: SU.LPBK Register Description: Ethernet Interface Loopback Con

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 179 of 344 Register Name: SU.TFRC Register Description: Transmit Frame Resend Control R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 18 of 344 4 ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 180 of 344 Register Name: SU.TFSL Register Description: Transmit Frame Status Low Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 181 of 344 Register Name: SU.RFSB0 Register Description: Receive Frame Status Byte 0 Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 182 of 344 Register Name: SU.RFSB3 Register Description: Receive Frame Status Byte 3 Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 183 of 344 Register Name: SU.RMFSRL Register Description: Receiver Maximum Frame Low R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 184 of 344 Register Name: SU.QRIE Register Description: Receive Queue Cross Threshold e

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 185 of 344 Register Name: SU.RFRC Register Description: Receive Frame Rejection Control

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 186 of 344 11.6.2 MAC Registers The control Registers related to the control of the ind

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 187 of 344 Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission o

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 188 of 344 Register Name: SU.MACMIIA Register Description: MAC MII Management (MDIO) Ad

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 189 of 344 Register Name: SU.MACMIID Register Description: MAC MII (MDIO) Data Registe

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 19 of 344 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 190 of 344 Register Name: SU.MACFCR Register Description: MAC Flow Control Register Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 191 of 344 Register Name: SU.MMCCTRL Register Description: MAC MMC Control Register Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 192 of 344 Register Name: Reserved Register Description: MAC Reserved Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 193 of 344 Register Name: Reserved Register Description: MAC Reserved Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 194 of 344 Register Name: SU.RxFrmCtr Register Description: MAC All Frames Received Co

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 195 of 344 Register Name: SU.RxFrmOkCtr Register Description: MAC Frames Received OK C

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 196 of 344 Register Name: SU.TxFrmCtr Register Description: MAC All Frames Transmitted

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 197 of 344 Register Name: SU.TxBytesCtr Register Description: MAC All Bytes Transmitte

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 198 of 344 Register Name: SU.TxBytesOkCtr Register Description: MAC Bytes Transmitted

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 199 of 344 Register Name: SU.TxFrmUndr Register Description: MAC Transmit Frame Under

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2 of 344 TABLE OF CONTENTS 1 DESCRIPTION ...

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 20 of 344 6 BLOCK DIAGRAMS Figure 6-1. Main Block Diagram TTIPTRING RTIPRRING

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 200 of 344 Register Name: SU.TxBdFrmCtr Register Description: MAC All Frames Aborted C

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 201 of 344 11.7 T1/E1/J1 Transceiver Registers Register Name: TR.MSTRREG Register Des

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 202 of 344 Register Name: TR.IOCR1 Register Description: I/O Configuration Register 1 R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 203 of 344 Register Name: TR.IOCR2 Register Description: I/O Configuration Register 2

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 204 of 344 Register Name: TR.T1RCR1 Register Description: T1 Receive Control Register 1

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 205 of 344 Register Name: TR.T1RCR2 Register Description: T1 Receive Control Register 2

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 206 of 344 Register Name: TR.T1TCR1 Register Description: T1 Transmit Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 207 of 344 Register Name: TR.T1TCR2 Register Description: T1 Transmit Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 208 of 344 Register Name: TR.T1CCR1 Register Description: T1 Common Control Register 1

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 209 of 344 Register Name: TR.SSIE1 (E1 Mode) Register Description: Software Signaling I

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 21 of 344 Figure 6-2. Block Diagram of T1/E1/J1 Transceiver TXLIUCLOCKADAPTERBACK

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 210 of 344 Register Name: TR.SSIE3 (T1 Mode) Register Description: Software Signaling-I

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 211 of 344 Register Name: TR.T1RDMR1 Register Description: T1 Receive Digital-Milliwatt

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 212 of 344 Register Name: TR.IDR Register Description: Device Identification Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 213 of 344 Register Name: TR.INFO2 Register Description: Information Register 2 Registe

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 214 of 344 Register Name: TR.INFO3 Register Description: Information Register 3 Registe

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 215 of 344 Register Name: TR.SR1 Register Description: Status Register 1 Register Addre

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 216 of 344 Register Name: TR.IMR1 Register Description: Interrupt Mask Register 1 Regi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 217 of 344 Register Name: TR.SR2 Register Description: Status Register 2 Register Addre

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 218 of 344 Register Name: TR.IMR2 Register Description: Interrupt Mask Register 2 Regi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 219 of 344 Register Name: TR.SR3 Register Description: Status Register 3 Register Addr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 22 of 344 Figure 6-3. Receive and Transmit T1/E1/J1 LIU LOCAL LOOPBACKTRINGTTIPJITTER

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 220 of 344 Register Name: TR.IMR3 Register Description: Interrupt Mask Register 3 Regi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 221 of 344 Register Name: TR.SR4 Register Description: Status Register 4 Register Addr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 222 of 344 Register Name: TR.IMR4 Register Description: Interrupt Mask Register 4 Regi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 223 of 344 Register Name: TR.SR5 Register Description: Status Register 5 Register Addre

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 224 of 344 Register Name: TR.IMR5 Register Description: Interrupt Mask Register 5 Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 225 of 344 Register Name: TR.SR6, TR.SR7 Register Description: HDLC #1 Status Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 226 of 344 Register Name: TR.IMR6, TR.IMR7 Register Description: HDLC # 1 Interrupt M

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 227 of 344 Register Name: TR.INFO5, TR.INFO6 Register Description: HDLC #1 Informatio

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 228 of 344 Register Name: TR.SR8 Register Description: Status Register 8 Register Addre

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 229 of 344 Register Name: TR.SR9 Register Description: Status Register 9 Register Addre

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 23 of 344 Figure 6-4. Receive and Transmit T1/E1/J1 Framer RECEIVE FRAMERTRANSMIT FRAM

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 230 of 344 Register Name: TR.IMR9 Register Description: Interrupt Mask Register 9 Regi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 231 of 344 Register Name: TR.PCPR Register Description: Per-Channel Pointer Register Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 232 of 344 Register Name: TR.PCDR1 Register Description: Per-Channel Data Register 1 R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 233 of 344 Register Name: TR.INFO7 Register Description: Information Register 7 (Real-T

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 234 of 344 Register Name: TR.E1RCR1 Register Description: E1 Receive Control Register 1

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 235 of 344 Register Name: TR.E1TCR1 Register Description: E1 Transmit Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 236 of 344 Register Name: TR.E1TCR2 Register Description: E1 Transmit Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 237 of 344 Register Name: TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4 Register Descr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 238 of 344 Register Name: TR.SIGCR Register Description: Signaling Control Register Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 239 of 344 Register Name: TR.ERCNT Register Description: Error-Counter Configuration Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 24 of 344 Figure 6-5. T1/E1/J1 Backplane Interface RLINKRLCLKRSIGRSIGFRRSERORCLKORSYN

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 240 of 344 Register Name: TR.LCVCR1 Register Description: Line-Code Violation Count Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 241 of 344 Register Name: TR.FOSCR1 Register Description: Frames Out-of-Sync Count Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 242 of 344 Register Name: TR.LBCR Register Description: Loopback Control Register Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 243 of 344 Register Name: TR.PCLR1 Register Description: Per-Channel Loopback Enable Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 244 of 344 Register Name: TR.ESCR Register Description: Elastic Store Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 245 of 344 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 246 of 344 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 247 of 344 Register Name: TR.TS1 to TR.TS12 Register Description: Transmit Signaling R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 248 of 344 Register Name: TR.TS1 to TR.TS12 Register Description: Transmit Signaling R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 249 of 344 Register Name: TR.RS1 to TR.RS12 Register Description: Receive Signaling Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 25 of 344 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 250 of 344 Register Name: TR.RS1 to TR.RS16 Register Description: Receive Signaling Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 251 of 344 Register Name: TR.CCR1 Register Description: Common Control Register 1 Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 252 of 344 Register Name: TR.CCR2 Register Description: Common Control Register 2 Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 253 of 344 Register Name: TR.CCR4 Register Description: Common Control Register 4 Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 254 of 344 Register Name: TR.TDS0M Register Description: Transmit DS0 Monitor Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 255 of 344 Register Name: TR.LIC1 Register Description: Line Interface Control 1 Regist

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 256 of 344 Register Name: TR.TLBC Register Description: Transmit Line Build-Out Control

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 257 of 344 Register Name: TR.LIC2 Register Description: Line Interface Control 2 Regist

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 258 of 344 Register Name: TR.LIC3 Register Description: Line Interface Control 3 Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 259 of 344 Register Name: TR.LIC4 Register Description: Line Interface Control 4 Regist

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 26 of 344 NAME PIN TYPE FUNCTION RD/DS B11 I Read Data Strobe (Intel Mode): The DS33R1

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 260 of 344 Register Name: TR.IAAR Register Description: Idle Array Address Register Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 261 of 344 Register Name: TR.TCICE2 Register Description: Transmit-Channel Idle-Code En

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 262 of 344 Register Name: TR.RCICE2 Register Description: Receive-Channel Idle-Code Ena

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 263 of 344 Register Name: TR.RCBR2 Register Description: Receive Channel Blocking Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 264 of 344 Register Name: TR.TCBR1 Register Description: Transmit Channel Blocking Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 265 of 344 Register Name: TR.H1TC, TR.H2TC Register Description: HDLC #1 Transmit Contr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 266 of 344 Register Name: TR.H1FC, TR.H2FC Register Description: HDLC # 1 FIFO Control

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 267 of 344 Register Name: TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 TR.H2RCS1, TR.H2RC

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 268 of 344 Register Name: TR.H1RTSBS, TR.H2RTSBS Register Description: HDLC # 1 Recei

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 269 of 344 Register Name: TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 TR.H2TCS1, TR.H2TC

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 27 of 344 NAME PIN TYPE FUNCTION MII/RMII PHY PORT COL_DET N18 I Collision Detect (MI

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 270 of 344 Register Name: TR.H1TTSBS, TR.H2TTSBS Register Description: HDLC # 1 Trans

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 271 of 344 Register Name: TR.H1TF, TR.H2TF Register Description: HDLC # 1 Transmit FIFO

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 272 of 344 Register Name: TR.H1TFBA, TR.H2TFBA Register Description: HDLC # 1 Transmit

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 273 of 344 Register Name: TR.TCD1 Register Description: Transmit Code-Definition Regis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 274 of 344 Register Name: TR.RUPCD1 Register Description: Receive Up-Code Definition R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 275 of 344 Register Name: TR.RDNCD1 Register Description: Receive Down-Code Definition

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 276 of 344 Register Name: TR.RSCC Register Description: In-Band Receive Spare Control

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 277 of 344 Register Name: TR.RSCD1 Register Description: Receive Spare-Code Definition

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 278 of 344 Register Name: TR.RFDL (TR.BOCC.4 = 1) Register Description: Receive FDL Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 279 of 344 Register Name: TR.TFDL Register Description: Transmit FDL Register Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 28 of 344 NAME PIN TYPE FUNCTION TXD[0] F19 TXD[1] F18 TXD[2] E20 TXD[3] E19 O Transmi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 280 of 344 Register Name: TR.RAF Register Description: Receive Align Frame Register Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 281 of 344 Register Name: TR.RSiAF Register Description: Received Si Bits of the Align

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 282 of 344 Register Name: TR.RRA Register Description: Received Remote Alarm Register A

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 283 of 344 Register Name: TR.RSa5 Register Description: Received Sa5 Bits Register Addr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 284 of 344 Register Name: TR.RSa7 Register Description: Received Sa7 Bits Register Addr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 285 of 344 Register Name: TR.TAF Register Description: Transmit Align Frame Register Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 286 of 344 Register Name: TR.TSiAF Register Description: Transmit Si Bits of the Align

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 287 of 344 Register Name: TR.TRA Register Description: Transmit Remote Alarm Register A

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 288 of 344 Register Name: TR.TSa5 Register Description: Transmitted Sa5 Bits Register A

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 289 of 344 Register Name: TR.TSa7 Register Description: Transmit Sa7 Bits Register Addr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 29 of 344 NAME PIN TYPE FUNCTION PHY MANAGEMENT BUS MDC C19 O Management Data Clock (M

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 290 of 344 Register Name: TR.TSACR Register Description: Transmit Sa Bit Control Regist

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 291 of 344 Register Name: TR.BRP1 Register Description: BERT Repetitive Pattern Set Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 292 of 344 Register Name: TR.BC1 Register Description: BERT Control Register 1 Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 293 of 344 Register Name: TR.BC2 Register Description: BERT Control Register 2 Registe

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 294 of 344 Register Name: TR.BBC1 Register Description: BERT Bit Count Register 1 Regi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 295 of 344 Register Name: TR.BEC1 Register Description: BERT Error-Count Register 1 Reg

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 296 of 344 Register Name: TR.BIC Register Description: BERT Interface Control Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 297 of 344 Register Name: TR.ERC Register Description: Error-Rate Control Register Regi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 298 of 344 Register Name: TR.NOE1 Register Description: Number-of-Errors 1 Register Add

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 299 of 344 11.7.1 Number-of-Errors Left Register The host can read the TR.NOELx regist

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 3 of 344 9.14.1 DTE and DCE Mode ...

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 30 of 344 NAME PIN TYPE FUNCTION SDATA[0] W2 SDATA[1] Y4 SDATA[2] Y2 SDATA[3] Y5 SDATA

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 300 of 344 12 FUNCTIONAL TIMING 12.1 Functional Serial I/O Timing The Serial Interface

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 301 of 344 The DS33R11 provides the TBSYNC signal as a byte boundary indication to an e

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 302 of 344 In Half-Duplex (DTE) Mode, the DS33R11 supports CRS and COL signals. CRS is

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 303 of 344 RMII Receive data on RXD[1:0] is expected to be synchronous with the rising

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 304 of 344 Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 305 of 344 Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 306 of 344 Figure 12-16. Transmit-Side ESF Timing 123456789101112123TS

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 307 of 344 Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 308 of 344 12.4 E1 Mode Figure 12-20. Receive-Side Timing FRAME#1234567891

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 309 of 344 Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enab

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 31 of 344 NAME PIN TYPE FUNCTION T1/E1/J1 ANALOG LINE INTERFACE TTIP R1, R2 O Transmit

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 310 of 344 Figure 12-24. G.802 Timing, E1 Mode Only 12345678

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 311 of 344 Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 312 of 344 Figure 12-28. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Sto

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 313 of 344 13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 314 of 344 13.1 Thermal Characteristics Table 13-3. Thermal Characteristics PARAMET

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 315 of 344 13.2 MII Interface Table 13-5. Transmit MII Interface (Note 1, Figure 13-1

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 316 of 344 Table 13-6. Receive MII Interface (Note 1, Figure 13-2) 10Mbps 100Mbps PARA

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 317 of 344 13.3 RMII Interface Table 13-7. Transmit RMII Interface (Note 1, Figure 13

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 318 of 344 Table 13-8. Receive RMII Interface (Note 1, Figure 13-4) 10Mbps 100Mbps PAR

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 319 of 344 13.4 MDIO Interface Table 13-9. MDIO Interface (Note 1, Figure 13-5) PARAME

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 32 of 344 NAME PIN TYPE FUNCTION TSIG B4 I Transmit Signaling Input for the T1/E1/J1 T

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 320 of 344 13.5 Transmit WAN Interface Table 13-10. Transmit WAN Interface (Note 1, F

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 321 of 344 13.6 Receive WAN Interface Table 13-11. Receive WAN Interface (Note 1, Fig

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 322 of 344 13.7 SDRAM Timing Table 13-12. SDRAM Interface Timing (Note 1, Figure 13-8)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 323 of 344 Figure 13-8. SDRAM Interface Timing SDCLKO(output)SDATA(output)t1SDATA(i

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 324 of 344 13.8 Microprocessor Bus AC Characteristics Table 13-13. AC Characteristics

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 325 of 344 Figure 13-9. Intel Bus Read Timing (MODEC = 00) t2 t3Address ValidData Val

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 326 of 344 Figure 13-11. Motorola Bus Read Timing (MODEC = 01) t2 t3Address ValidDat

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 327 of 344 13.9 AC Characteristics: Receive-Side Table 13-14. AC Characteristics: Re

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 328 of 344 Figure 13-13. Receive-Side Timing tD11tD2RSERO /

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 329 of 344 Figure 13-14. Receive-Side Timing, Elastic Store Enabled

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 33 of 344 NAME PIN TYPE FUNCTION RSYNC G4 I/O Receive Sync for the T1/E1/J1 Transceive

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 330 of 344 Figure 13-15. Receive Line Interface Timing tFtRRPOSI, RNEGIRDCLKICLttCP

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 331 of 344 13.10 AC Characteristics: Backplane Clock Timing Table 13-15. AC Character

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 332 of 344 13.11 AC Characteristics: Transmit Side Table 13-16. AC Characteristics:

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 333 of 344 Figure 13-17. Transmit-Side Timing tFtR1

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 334 of 344 Figure 13-18. Transmit-Side Timing, Elastic Store Enabled

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 335 of 344 13.12 JTAG Interface Timing Table 13-17. JTAG Interface Timing (VDD3.3 = 3

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 336 of 344 14 JTAG INFORMATION The DS33R11 contains two JTAG ports. Port 1 is for the

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 337 of 344 14.1 JTAG TAP Controller State Machine Description This section covers the

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 338 of 344 Update-DR A falling edge on JTCLK while in the Update-DR state will latch t

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 339 of 344 Figure 14-2. TAP Controller State Diagram 1001111111111110000010000110000S

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 34 of 344 NAME PIN TYPE FUNCTION ETHERNET MAPPER RECEIVE SERIAL INTERFACE RSERI H1 I R

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 340 of 344 Table 14-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SEL

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 341 of 344 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE REVISION ID[31:28]

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 342 of 344 14.5 JTAG Functional Timing This functional timing for the JTAG circuits s

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 343 of 344 15 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not r

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 344 of 344 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circu

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 35 of 344 NAME PIN TYPE FUNCTION TDCLKO C2 O Transmit Clock Output from the T1/E1/J1 F

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 36 of 344 NAME PIN TYPE FUNCTION HARDWARE AND STATUS PINS LIUC B2 I Line Interface Uni

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 37 of 344 NAME PIN TYPE FUNCTION SYSTEM CLOCKS SYSCLKI V8 I System Clock In for Ether

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 38 of 344 NAME PIN TYPE FUNCTION JTAG INTERFACE JTCLK1 A7 Ipu JTAG Clock 1 for the Eth

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 39 of 344 NAME PIN TYPE FUNCTION POWER SUPPLIES RVDD K3, L1 — Receive Analog Positive

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 4 of 344 10.17.4 FIFO Information...

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 40 of 344 Figure 7-1. 256-Ball BGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 41 of 344 8 FUNCTIONAL DESCRIPTION The DS33R11 provides interconnection and mapping fun

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 42 of 344 Both the transmit and receive path of the integrated T1/E1/J1 transceiver als

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 43 of 344 9 ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R11 clocks sources and

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 44 of 344 Figure 9-1. Clocking for the DS33R11 TTIPTRING RTIPRRINGSYSCLKI

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 45 of 344 9.1.1 Ethernet Interface Clock Modes The Ethernet PHY interface has several

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 46 of 344 9.2 Resets and Low Power Modes The external RST pin and the global reset bit

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 47 of 344 9.3 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE:

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 48 of 344 9.6 Device Interrupts Figure 9-2 diagrams the flow of interrupt conditions fr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 49 of 344 Figure 9-2. Device Interrupt Information Flow Diagram Receive FCS Errored Pa

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 5 of 344 12.4 E1 MODE...

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 50 of 344 9.7 Interrupt Information Registers The interrupt information registers prov

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 51 of 344 9.11 Connections and Queues The multi-port devices in this product family pr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 52 of 344 It is recommended that the user reset the queue pointers for the connection a

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 53 of 344 9.13 Flow Control Flow control may be required to ensure that data queues do

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 54 of 344 9.13.1 Full Duplex Flow Control Automatic flow control is enabled by default

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 55 of 344 Figure 9-3. Flow Control Using Pause Control Frame Receive QueueGrowthReceive

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 56 of 344 9.14 Ethernet Interface Port The Ethernet port interface allows for direct c

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 57 of 344 The MAC circuitry generates a frame status for every frame that is received.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 58 of 344 9.14.1 DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 59 of 344 Figure 9-6. DS33R11 Configured as a DCE in MII Mode MACTXD[3:0]RXD[3:0]TX_CLK

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 6 of 344 LIST OF FIGURES Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 60 of 344 Table 9-6. MAC Control Registers ADDRESS REGISTER DESCRIPTION 0000h-0003h S

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 61 of 344 9.15.1 MII Mode Options The Ethernet interface can be configured for MII ope

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 62 of 344 9.15.3 PHY MII Management Block and MDIO Interface The MII Management Block

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 63 of 344 9.16.1 Receive Data Interface 9.16.1.1 Receive Pattern Detection The Receiv

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 64 of 344 9.16.2 Repetitive Pattern Synchronization Repetitive pattern synchronization

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 65 of 344 9.16.4.1 Error Insertion Error insertion inserts errors into the outgoing pat

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 66 of 344 9.18 Receive Packet Processor The Receive Packet Processor accepts data from

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 67 of 344 Bit reordering changes the bit order of each byte. If bit reordering is disab

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 68 of 344 9.19 X.86 Encoding and Decoding X.86 protocol provides a method for encapsul

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 69 of 344 Figure 9-13. X.86 Encapsulation of the MAC frame Flag(0x7E)Address(0x04)Contr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 7 of 344 Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 70 of 344 The X86 received frame is aborted if: • If 7d,7E is detected. This is an ab

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 71 of 344 9.20 Committed Information Rate Controller The DS33R11 provides a CIR provis

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 72 of 344 10 INTEGRATED T1/E1/J1 TRANSCEIVER 10.1 T1/E1/J1 Clocks Figure 10-1 shows the

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 73 of 344 Table 10-1. T1/E1/J1 Transmit Clock Source TCSS1 TCSS0 TRANSMIT CLOCK SOURC

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 74 of 344 10.4 T1 Framer/Formatter Control and Status The T1 framer portion of the tr

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 75 of 344 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digit

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 76 of 344 10.5 E1 Framer/Formatter Control and Status The E1 framer portion of the tra

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 77 of 344 10.5.1 Automatic Alarm Generation The device can be programmed to automatica

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 78 of 344 10.7 Error Counters The transceiver contains four counters that are used t

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 79 of 344 10.7.2 Path Code Violation Count Register (TR.PCVCR) In T1 mode, the path co

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 8 of 344 LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ...

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 80 of 344 10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) In T1 mode, TR.FOSCR is

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 81 of 344 10.8 DS0 Monitoring Function The transceiver has the ability to monitor one

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 82 of 344 10.9 Signaling Operation There are two methods to access receive signaling

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 83 of 344 10.9.2 Hardware-Based Receive Signaling In hardware-based signaling the sig

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 84 of 344 Figure 10-3. Simplified Diagram of Transmit Signaling Path

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 85 of 344 10.9.3.2 E1 Mode In E1 mode, TS16 carries the signaling information. This in

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 86 of 344 10.10 Per-Channel Idle Code Generation Channel data can be replaced by an i

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 87 of 344 10.10.1 Idle-Code Programming Examples Example 1 Sets transmit channel 3 i

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 88 of 344 10.11 Channel Blocking Registers The receive channel blocking registers (TR.

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 89 of 344 10.12.2 Transmit Elastic Store See the TR.IOCR1 and TR.IOCR2 registers for i

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9 of 344 1 DESCRIPTION The DS33R11 provides interconnection and mapping functionality b

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 90 of 344 10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The device can implem

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 91 of 344 10.14 T1 Bit-Oriented Code (BOC) Controller The transceiver contains a BOC g

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 92 of 344 10.15 Additional (Sa) and International (Si) Bit Operation (E1 Only) When op

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 93 of 344 10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver This device has tw

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 94 of 344 Table 10-12. HDLC Controller Registers REGISTER FUNCTION CONTROL AND CONFIGU

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 95 of 344 10.16.2 FIFO Control The FIFO control register (TR.HxFC) controls and sets th

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 96 of 344 10.16.4 FIFO Information The transmit FIFO buffer-available register indicat

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 97 of 344 10.17 Legacy FDL Support (T1 Mode) 10.17.1 Overview To provide backward comp

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 98 of 344 10.17.3 Transmit Section The transmit section shifts out into the T1 data str

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 99 of 344 10.19 Programmable In-Band Loop Code Generation and Detection The transceiv